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[src/trunk]: src/sys/arch Adjust egister usage so that r4 and r5 are preserve...



details:   https://anonhg.NetBSD.org/src/rev/3609aa64bae2
branches:  trunk
changeset: 1016479:3609aa64bae2
user:      skrll <skrll%NetBSD.org@localhost>
date:      Sat Nov 21 19:57:35 2020 +0000

description:
Adjust egister usage so that r4 and r5 are preserved as cur{cpu,lwp}
respectively as required by the change to make ASTs operate per-LWP
rather than per-CPU.  DO_AST_AND_RESTORE_ALIGNMENT_FAULTS expects this.

Remove the call to dosoftints while I'm here as it's dont in DO_AST...

XXX untested

diffstat:

 sys/arch/arm/ofw/ofw_irq.S       |  21 ++++++++++-----------
 sys/arch/arm/sa11x0/sa11x0_irq.S |  25 +++++++++++--------------
 sys/arch/shark/isa/isa_irq.S     |  22 +++++++++-------------
 3 files changed, 30 insertions(+), 38 deletions(-)

diffs (270 lines):

diff -r a6b92014b45e -r 3609aa64bae2 sys/arch/arm/ofw/ofw_irq.S
--- a/sys/arch/arm/ofw/ofw_irq.S        Sat Nov 21 19:55:49 2020 +0000
+++ b/sys/arch/arm/ofw/ofw_irq.S        Sat Nov 21 19:57:35 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ofw_irq.S,v 1.16 2020/11/21 09:36:27 skrll Exp $       */
+/*     $NetBSD: ofw_irq.S,v 1.17 2020/11/21 19:57:35 skrll Exp $       */
 
 /*
  * Copyright (c) 1994-1998 Mark Brinicombe.
@@ -95,12 +95,13 @@
  * Regsister usage
  *
  *  r4 - Address of cpu_info (on entry)
- *  r5  - Pointer to handler pointer list
+ *  r5  - Address of curlwp
  *  r6  - Address of current handler
  *  r7  - pspr mode (must be preserved)
  *  r8  - Current IRQ requests.
  *  r9  - Used to count through possible IRQ bits.
  *  r10 - Base address of IOMD
+ *  r11  - Pointer to handler pointer list
  */
 
 ASENTRY_NP(irq_entry)
@@ -188,7 +189,7 @@
 #ifdef EXEC_AOUT
        ldr     r0, [sp]                /* Fetch SPSR */
 #endif
-       ENABLE_ALIGNMENT_FAULTS
+       ENABLE_ALIGNMENT_FAULTS         /* puts cur{cpu,lwp} in r4/r5 */
 
        mov     r8, #0x00000001         /* timer interrupt pending! */
        mov     r8, r8, lsl #IRQ_TIMER0
@@ -224,17 +225,17 @@
         */
 
        mov     r9, #(NIPL - 1)
-       ldr     r5, Lspl_masks
+       ldr     r11, Lspl_masks
 
 Lfind_highest_ipl:
-       ldr     r2, [r5, r9, lsl #2]
+       ldr     r2, [r11, r9, lsl #2]
        tst     r8, r2
        subeq   r9, r9, #1
        beq     Lfind_highest_ipl
 
        /* r9 = SPL level of highest priority interrupt */
        add     r9, r9, #1
-       ldr     r2, [r5, r9, lsl #2]
+       ldr     r2, [r11, r9, lsl #2]
        mvn     r2, r2
        orr     r0, r0, r2
 
@@ -252,7 +253,7 @@
        bic     r0, r0, #I32_bit
        msr     cpsr_all, r0
 
-       ldr     r5, Lirqhandlers
+       ldr     r11, Lirqhandlers
        mov     r9, #0x00000001
 
 irqloop:
@@ -260,7 +261,7 @@
        tst     r8, r9                  /* Is a bit set ? */
        beq     nextirq                 /* No ? try next bit */
 
-       ldr     r6, [r5]                /* Get address of first handler structure */
+       ldr     r6, [r11]               /* Get address of first handler structure */
 
        teq     r6, #0x00000000         /* Do we have a handler */
        moveq   r0, r8                  /* IRQ requests as arg 0 */
@@ -301,7 +302,7 @@
        stmia   r3, {r1-r2}             /* store ev_count */
 
 nextirq:
-       add     r5, r5, #0x00000004     /* update pointer to handlers */
+       add     r11, r11, #0x00000004   /* update pointer to handlers */
        mov     r9, r9, lsl #1          /* move on to next bit */
        teq     r9, #(1 << 24)          /* done the last bit ? */
        bne     irqloop                 /* no - loop back. */
@@ -315,8 +316,6 @@
        str     r2, [r1]
        bl      _C_LABEL(irq_setmasks)
 
-       bl      _C_LABEL(dosoftints)    /* Handle the soft interrupts */
-
        /* Kill IRQ's in preparation for exit */
        mrs     r0, cpsr
        orr     r0, r0, #(I32_bit)
diff -r a6b92014b45e -r 3609aa64bae2 sys/arch/arm/sa11x0/sa11x0_irq.S
--- a/sys/arch/arm/sa11x0/sa11x0_irq.S  Sat Nov 21 19:55:49 2020 +0000
+++ b/sys/arch/arm/sa11x0/sa11x0_irq.S  Sat Nov 21 19:57:35 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: sa11x0_irq.S,v 1.19 2020/11/21 09:36:27 skrll Exp $    */
+/*     $NetBSD: sa11x0_irq.S,v 1.20 2020/11/21 19:59:10 skrll Exp $    */
 
 /*
  * Copyright (c) 1998 Mark Brinicombe.
@@ -72,20 +72,21 @@
 /*
  * Register usage
  *
- *  r4  - Pointer to cpu_info
- *  r5  - Pointer to handler pointer list
+ *  r4  - Pointer to curcpu
+ *  r5  - pointer to curlwp
  *  r6  - Address of current handler
  *  r7 - pspr mode
  *  r8  - Current IRQ requests.
  *  r9  - Used to count through possible IRQ bits.
  *  r10 - Base address of SAIP
+ *  r11 - Pointer to handler pointer list
  */
 
 ASENTRY_NP(irq_entry)
        sub     lr, lr, #0x00000004     /* Adjust the lr */
 
        PUSHFRAMEINSVC                  /* Push an interrupt frame */
-       ENABLE_ALIGNMENT_FAULTS
+       ENABLE_ALIGNMENT_FAULTS         /* puts cur{cpu,lwp} in r4/r5 */
 
        /* Load r8 with the SAIPIC interrupt requests */
 
@@ -123,17 +124,17 @@
         */
 
        mov     r9, #(NIPL - 1)
-       ldr     r5, Lspl_masks
+       ldr     r11, Lspl_masks
 
 Lfind_highest_ipl:
-       ldr     r2, [r5, r9, lsl #2]
+       ldr     r2, [r11, r9, lsl #2]
        tst     r8, r2
        subeq   r9, r9, #1
        beq     Lfind_highest_ipl
 
        /* r9 = SPL level of highest priority interrupt */
        add     r9, r9, #1
-       ldr     r2, [r5, r9, lsl #2]
+       ldr     r2, [r11, r9, lsl #2]
 
        ldr     r1, [r4, #CI_CPL]
        str     r9, [r4, #CI_CPL]
@@ -154,7 +155,7 @@
        bic     r0, r0, #I32_bit
        msr     cpsr_all, r0
 
-       ldr     r5, Lirqhandlers
+       ldr     r11, Lirqhandlers
         mov    r9, #0x00000001
 
 irqloop:
@@ -162,7 +163,7 @@
        tst     r8, r9                  /* Is a bit set ? */
        beq     nextirq                 /* No ? try next bit */
 
-       ldr     r6, [r5]                /* Get address of first handler structure */
+       ldr     r6, [r11]               /* Get address of first handler structure */
 
        teq     r6, #0x00000000         /* Do we have a handler */
        moveq   r0, r8                  /* IRQ requests as arg 0 */
@@ -218,7 +219,7 @@
 
 irqdone:
 nextirq:
-       add     r5, r5, #0x00000004     /* update pointer to handlers */
+       add     r11, r11, #0x00000004   /* update pointer to handlers */
        mov     r9, r9, lsl #1          /* move on to next bit */
        teq     r9, #(1 << 31)          /* done the last bit ? */
        bne     irqloop                 /* no - loop back. */
@@ -229,10 +230,6 @@
        /* Restore previous disabled mask */
        bl      _C_LABEL(irq_setmasks)
 
-#ifdef __HAVE_FAST_SOFTINTS
-       bl      _C_LABEL(dosoftints)    /* Handle the soft interrupts */
-#endif
-
        /* Kill IRQ's in preparation for exit */
         mrs     r0, cpsr
         orr     r0, r0, #(I32_bit)
diff -r a6b92014b45e -r 3609aa64bae2 sys/arch/shark/isa/isa_irq.S
--- a/sys/arch/shark/isa/isa_irq.S      Sat Nov 21 19:55:49 2020 +0000
+++ b/sys/arch/shark/isa/isa_irq.S      Sat Nov 21 19:57:35 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: isa_irq.S,v 1.17 2018/01/30 19:22:28 skrll Exp $       */
+/*     $NetBSD: isa_irq.S,v 1.18 2020/11/21 19:58:11 skrll Exp $       */
 
 /*
  * Copyright 1997
@@ -113,8 +113,8 @@
 /*
  * Register usage
  *
- *  r5  - Pointer to handler pointer list
  *  r6  - Address of current handler
+ *  r7  - Pointer to handler pointer list
  *  r8  - Current IRQ requests.
  *  r9  - Used to count through possible IRQ bits.
  *  r10 - Base address of IOMD
@@ -125,7 +125,7 @@
        sub     lr, lr, #0x00000004     /* Adjust the lr */
 
        PUSHFRAMEINSVC                  /* Push an interrupt frame */
-       ENABLE_ALIGNMENT_FAULTS         /* cpuinfo is in r4 after execution */
+       ENABLE_ALIGNMENT_FAULTS         /* puts cur{cpu,lwp} in r4/r5 */
 
        /* Load r8 with the ISA 8259 irqs */
        /* r8 <- irq's pending [15:0] */
@@ -183,17 +183,17 @@
         */
 
        mov     r9, #(NIPL - 1)
-       ldr     r5, .Lspl_masks
+       ldr     r7, .Lspl_masks
 
 .Lfind_highest_ipl:
-       ldr     r2, [r5, r9, lsl #2]
+       ldr     r2, [r7, r9, lsl #2]
        tst     r8, r2
        subeq   r9, r9, #1
        beq     .Lfind_highest_ipl
 
        /* r9 = SPL level of highest priority interrupt */
        add     r9, r9, #1
-       ldr     r2, [r5, r9, lsl #2]
+       ldr     r2, [r7, r9, lsl #2]
        mvn     r2, r2
        orr     r0, r0, r2
 
@@ -210,7 +210,7 @@
        bic     r0, r0, #I32_bit
        msr     cpsr_all, r0
 
-       ldr     r5, .Lirqhandlers
+       ldr     r7, .Lirqhandlers
        mov     r9, #0x00000001
 
 irqloop:
@@ -218,7 +218,7 @@
        tst     r8, r9                  /* Is a bit set ? */
        beq     nextirq                 /* No ? try next bit */
 
-       ldr     r6, [r5]                /* Get address of first handler structure */
+       ldr     r6, [r7]                /* Get address of first handler structure */
 
        teq     r6, #0x00000000         /* Do we have a handler */
        moveq   r0, r8                  /* IRQ requests as arg 0 */
@@ -255,7 +255,7 @@
        stmia   r3, {r1-r2}             /* store ev_count */
 
 nextirq:
-       add     r5, r5, #0x00000004     /* update pointer to handlers */
+       add     r7, r7, #0x00000004     /* update pointer to handlers */
        mov     r9, r9, lsl #1          /* move on to next bit */
        teq     r9, #(1 << 16)          /* done the last bit ? */
        bne     irqloop                 /* no - loop back. */
@@ -269,10 +269,6 @@
        str     r2, [r1]
        bl      _C_LABEL(irq_setmasks)
 
-#ifdef __HAVE_FAST_SOFTINTS
-       bl      _C_LABEL(dosoftints)    /* Handle the soft interrupts */
-#endif
-
        /* Kill IRQ's in preparation for exit */
        mrs     r0, cpsr
        orr     r0, r0, #(I32_bit)



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