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[src/trunk]: src/sys/arch/mips Remove 2 CPU limit in OCTEON interrupt control...



details:   https://anonhg.NetBSD.org/src/rev/84434a23608c
branches:  trunk
changeset: 1011959:84434a23608c
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Fri Jul 17 21:59:30 2020 +0000

description:
Remove 2 CPU limit in OCTEON interrupt controller driver.

diffstat:

 sys/arch/mips/cavium/dev/octeon_ciureg.h |   14 +-
 sys/arch/mips/cavium/octeon_cpunode.c    |    7 +-
 sys/arch/mips/cavium/octeon_intr.c       |  269 ++++++++++--------------------
 sys/arch/mips/cavium/octeonvar.h         |   26 +-
 sys/arch/mips/mips/cpu_subr.c            |    9 +-
 5 files changed, 128 insertions(+), 197 deletions(-)

diffs (truncated from 600 to 300 lines):

diff -r f0769051ecef -r 84434a23608c sys/arch/mips/cavium/dev/octeon_ciureg.h
--- a/sys/arch/mips/cavium/dev/octeon_ciureg.h  Fri Jul 17 21:04:14 2020 +0000
+++ b/sys/arch/mips/cavium/dev/octeon_ciureg.h  Fri Jul 17 21:59:30 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: octeon_ciureg.h,v 1.9 2020/06/22 12:26:11 simonb Exp $ */
+/*     $NetBSD: octeon_ciureg.h,v 1.10 2020/07/17 21:59:30 jmcneill Exp $      */
 
 /*
  * Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -39,17 +39,23 @@
 #define        CIU_INT1_SUM0                           UINT64_C(0x0001070000000008)
 #define        CIU_INT2_SUM0                           UINT64_C(0x0001070000000010)
 #define        CIU_INT3_SUM0                           UINT64_C(0x0001070000000018)
+#define        CIU_IP2_SUM0(n)                         (CIU_INT0_SUM0 + 0x10 * (n))
+#define        CIU_IP3_SUM0(n)                         (CIU_INT1_SUM0 + 0x10 * (n))
 #define        CIU_INT32_SUM0                          UINT64_C(0x0001070000000100)
 #define        CIU_INT_SUM1                            UINT64_C(0x0001070000000108)
 #define        CIU_INT0_EN0                            UINT64_C(0x0001070000000200)
 #define        CIU_INT1_EN0                            UINT64_C(0x0001070000000210)
 #define        CIU_INT2_EN0                            UINT64_C(0x0001070000000220)
 #define        CIU_INT3_EN0                            UINT64_C(0x0001070000000230)
+#define        CIU_IP2_EN0(n)                          (CIU_INT0_EN0 + 0x20 * (n))
+#define        CIU_IP3_EN0(n)                          (CIU_INT1_EN0 + 0x20 * (n))
 #define        CIU_INT32_EN0                           UINT64_C(0x0001070000000400)
 #define        CIU_INT0_EN1                            UINT64_C(0x0001070000000208)
 #define        CIU_INT1_EN1                            UINT64_C(0x0001070000000218)
 #define        CIU_INT2_EN1                            UINT64_C(0x0001070000000228)
 #define        CIU_INT3_EN1                            UINT64_C(0x0001070000000238)
+#define        CIU_IP2_EN1(n)                          (CIU_INT0_EN1 + 0x20 * (n))
+#define        CIU_IP3_EN1(n)                          (CIU_INT1_EN1 + 0x20 * (n))
 #define        CIU_INT32_EN1                           UINT64_C(0x0001070000000408)
 #define        CIU_TIM0                                UINT64_C(0x0001070000000480)
 #define        CIU_TIM1                                UINT64_C(0x0001070000000488)
@@ -59,10 +65,13 @@
 #define        CIU_WDOG(n)                             (CIU_WDOG0 + (n) * 8)
 #define        CIU_PP_POKE0                            UINT64_C(0x0001070000000580)
 #define        CIU_PP_POKE1                            UINT64_C(0x0001070000000588)
+#define        CIU_PP_POKE(n)                          (CIU_PP_POKE0 + (n) * 8)
 #define        CIU_MBOX_SET0                           UINT64_C(0x0001070000000600)
 #define        CIU_MBOX_SET1                           UINT64_C(0x0001070000000608)
+#define        CIU_MBOX_SET(n)                         (CIU_MBOX_SET0 + (n) * 8)
 #define        CIU_MBOX_CLR0                           UINT64_C(0x0001070000000680)
 #define        CIU_MBOX_CLR1                           UINT64_C(0x0001070000000688)
+#define        CIU_MBOX_CLR(n)                         (CIU_MBOX_CLR0 + (n) * 8)
 #define        CIU_PP_RST                              UINT64_C(0x0001070000000700)
 #define        CIU_PP_DBG                              UINT64_C(0x0001070000000708)
 #define        CIU_GSTOP                               UINT64_C(0x0001070000000710)
@@ -76,10 +85,13 @@
 #define        CIU_PCI_INTA                            UINT64_C(0x0001070000000750)
 #define        CIU_INT4_SUM0                           UINT64_C(0x0001070000000c00)
 #define        CIU_INT4_SUM1                           UINT64_C(0x0001070000000c08)
+#define        CIU_IP4_SUM0(n)                         (CIU_INT4_SUM0 + 0x10 * (n))
 #define        CIU_INT4_EN00                           UINT64_C(0x0001070000000c80)
 #define        CIU_INT4_EN01                           UINT64_C(0x0001070000000c88)
 #define        CIU_INT4_EN10                           UINT64_C(0x0001070000000c90)
 #define        CIU_INT4_EN11                           UINT64_C(0x0001070000000c98)
+#define        CIU_IP4_EN0(n)                          (CIU_INT4_EN00 + 0x10 * (n))
+#define        CIU_IP4_EN1(n)                          (CIU_INT4_EN01 + 0x10 * (n))
 
 #define        CIU_BASE                                UINT64_C(0x0001070000000000)
 
diff -r f0769051ecef -r 84434a23608c sys/arch/mips/cavium/octeon_cpunode.c
--- a/sys/arch/mips/cavium/octeon_cpunode.c     Fri Jul 17 21:04:14 2020 +0000
+++ b/sys/arch/mips/cavium/octeon_cpunode.c     Fri Jul 17 21:59:30 2020 +0000
@@ -29,7 +29,7 @@
 #define __INTR_PRIVATE
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(0, "$NetBSD: octeon_cpunode.c,v 1.13 2020/06/23 05:14:18 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_cpunode.c,v 1.14 2020/07/17 21:59:30 jmcneill Exp $");
 
 #include "locators.h"
 #include "cpunode.h"
@@ -55,6 +55,8 @@
 #include <mips/cavium/dev/octeon_ciureg.h>
 #include <mips/cavium/dev/octeon_corereg.h>
 
+extern struct cpu_softc octeon_cpu_softc[];
+
 struct cpunode_attach_args {
        const char *cnaa_name;
        int cnaa_cpunum;
@@ -291,7 +293,6 @@
                return;
        }
 #ifdef MULTIPROCESSOR
-       KASSERTMSG(cpunum == 1, "cpunum %d", cpunum);
        if (!kcpuset_isset(cpus_booted, cpunum)) {
                aprint_naive(" disabled\n");
                aprint_normal(" disabled (unresponsive)\n");
@@ -299,7 +300,7 @@
        }
        struct cpu_info * const ci = cpu_info_alloc(NULL, cpunum, 0, cpunum, 0);
 
-       ci->ci_softc = &octeon_cpu1_softc;
+       ci->ci_softc = &octeon_cpu_softc[cpunum];
        ci->ci_softc->cpu_ci = ci;
 
        cpu_cpunode_attach_common(self, ci);
diff -r f0769051ecef -r 84434a23608c sys/arch/mips/cavium/octeon_intr.c
--- a/sys/arch/mips/cavium/octeon_intr.c        Fri Jul 17 21:04:14 2020 +0000
+++ b/sys/arch/mips/cavium/octeon_intr.c        Fri Jul 17 21:59:30 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: octeon_intr.c,v 1.17 2020/07/17 19:40:47 jmcneill Exp $        */
+/*     $NetBSD: octeon_intr.c,v 1.18 2020/07/17 21:59:30 jmcneill Exp $        */
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
  * All rights reserved.
@@ -44,7 +44,7 @@
 #define __INTR_PRIVATE
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.17 2020/07/17 19:40:47 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.18 2020/07/17 21:59:30 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/cpu.h>
@@ -199,158 +199,79 @@
 
 kmutex_t octeon_intr_lock;
 
-#define X(a)   MIPS_PHYS_TO_XKPHYS(OCTEON_CCA_NONE, (a))
-
-struct cpu_softc octeon_cpu0_softc = {
-       .cpu_ci = &cpu_info_store,
-       .cpu_int0_sum0 = X(CIU_INT0_SUM0),
-       .cpu_int1_sum0 = X(CIU_INT1_SUM0),
-       .cpu_int2_sum0 = X(CIU_INT4_SUM0),
-
-       .cpu_int_sum1 = X(CIU_INT_SUM1),
-
-       .cpu_int0_en[0] = X(CIU_INT0_EN0),
-       .cpu_int1_en[0] = X(CIU_INT1_EN0),
-       .cpu_int2_en[0] = X(CIU_INT4_EN00),
-
-       .cpu_int0_en[1] = X(CIU_INT0_EN1),
-       .cpu_int1_en[1] = X(CIU_INT1_EN1),
-       .cpu_int2_en[1] = X(CIU_INT4_EN01),
-
-       .cpu_int32_en = X(CIU_INT32_EN0),
-
-       .cpu_wdog = X(CIU_WDOG0),
-       .cpu_pp_poke = X(CIU_PP_POKE0),
-
-#ifdef MULTIPROCESSOR
-       .cpu_mbox_set = X(CIU_MBOX_SET0),
-       .cpu_mbox_clr = X(CIU_MBOX_CLR0),
-#endif
-};
-
-#ifdef MULTIPROCESSOR
-/* XXX limit of two CPUs ... */
-struct cpu_softc octeon_cpu1_softc = {
-       .cpu_int0_sum0 = X(CIU_INT2_SUM0),
-       .cpu_int1_sum0 = X(CIU_INT3_SUM0),
-       .cpu_int2_sum0 = X(CIU_INT4_SUM1),
-
-       .cpu_int_sum1 = X(CIU_INT_SUM1),
-
-       .cpu_int0_en[0] = X(CIU_INT2_EN0),
-       .cpu_int1_en[0] = X(CIU_INT3_EN0),
-       .cpu_int2_en[0] = X(CIU_INT4_EN10),
-
-       .cpu_int0_en[1] = X(CIU_INT2_EN1),
-       .cpu_int1_en[1] = X(CIU_INT3_EN1),
-       .cpu_int2_en[1] = X(CIU_INT4_EN11),
-
-       .cpu_int32_en = X(CIU_INT32_EN1),
-
-       .cpu_wdog = X(CIU_WDOG(1)),
-       .cpu_pp_poke = X(CIU_PP_POKE1),
-
-       .cpu_mbox_set = X(CIU_MBOX_SET1),
-       .cpu_mbox_clr = X(CIU_MBOX_CLR1),
-};
+#if defined(MULTIPROCESSOR)
+#define        OCTEON_NCPU     MAXCPUS
+#else
+#define        OCTEON_NCPU     1
 #endif
 
-#ifdef DEBUG
+struct cpu_softc octeon_cpu_softc[OCTEON_NCPU];
+
 static void
-octeon_mbox_test(void)
+octeon_intr_setup(void)
 {
-       const uint64_t mbox_clr0 = X(CIU_MBOX_CLR0);
-       const uint64_t mbox_clr1 = X(CIU_MBOX_CLR1);
-       const uint64_t mbox_set0 = X(CIU_MBOX_SET0);
-       const uint64_t mbox_set1 = X(CIU_MBOX_SET1);
-       const uint64_t int_sum0 = X(CIU_INT0_SUM0);
-       const uint64_t int_sum1 = X(CIU_INT2_SUM0);
-       const uint64_t sum_mbox_lo = __BIT(CIU_INT_MBOX_15_0);
-       const uint64_t sum_mbox_hi = __BIT(CIU_INT_MBOX_31_16);
+       struct cpu_softc *cpu;
+       int cpunum;
 
-       mips3_sd(mbox_clr0, ~0ULL);
-       mips3_sd(mbox_clr1, ~0ULL);
-
-       uint32_t mbox0 = mips3_ld(mbox_set0);
-       uint32_t mbox1 = mips3_ld(mbox_set1);
+#define X(a)   MIPS_PHYS_TO_XKPHYS(OCTEON_CCA_NONE, (a))
 
-       KDASSERTMSG(mbox0 == 0, "mbox0 %#x mbox1 %#x", mbox0, mbox1);
-       KDASSERTMSG(mbox1 == 0, "mbox0 %#x mbox1 %#x", mbox0, mbox1);
-
-       mips3_sd(mbox_set0, __BIT(0));
+       for (cpunum = 0; cpunum < OCTEON_NCPU; cpunum++) {
+               cpu = &octeon_cpu_softc[cpunum];
 
-       mbox0 = mips3_ld(mbox_set0);
-       mbox1 = mips3_ld(mbox_set1);
-
-       KDASSERTMSG(mbox0 == 1, "mbox0 %#x mbox1 %#x", mbox0, mbox1);
-       KDASSERTMSG(mbox1 == 0, "mbox0 %#x mbox1 %#x", mbox0, mbox1);
+               cpu->cpu_ip2_sum0 = X(CIU_IP2_SUM0(cpunum));
+               cpu->cpu_ip3_sum0 = X(CIU_IP3_SUM0(cpunum));
+               cpu->cpu_ip4_sum0 = X(CIU_IP4_SUM0(cpunum));
 
-       uint64_t sum0 = mips3_ld(int_sum0);
-       uint64_t sum1 = mips3_ld(int_sum1);
-
-       KDASSERTMSG((sum0 & sum_mbox_lo) != 0, "sum0 %#"PRIx64, sum0);
-       KDASSERTMSG((sum0 & sum_mbox_hi) == 0, "sum0 %#"PRIx64, sum0);
+               cpu->cpu_int_sum1 = X(CIU_INT_SUM1);
 
-       KDASSERTMSG((sum1 & sum_mbox_lo) == 0, "sum1 %#"PRIx64, sum1);
-       KDASSERTMSG((sum1 & sum_mbox_hi) == 0, "sum1 %#"PRIx64, sum1);
-
-       mips3_sd(mbox_clr0, mbox0);
-       mbox0 = mips3_ld(mbox_set0);
-       KDASSERTMSG(mbox0 == 0, "mbox0 %#x", mbox0);
-
-       mips3_sd(mbox_set0, __BIT(16));
+               cpu->cpu_ip2_en[0] = X(CIU_IP2_EN0(cpunum));
+               cpu->cpu_ip3_en[0] = X(CIU_IP3_EN0(cpunum));
+               cpu->cpu_ip4_en[0] = X(CIU_IP4_EN0(cpunum));
 
-       mbox0 = mips3_ld(mbox_set0);
-       mbox1 = mips3_ld(mbox_set1);
-
-       KDASSERTMSG(mbox0 == __BIT(16), "mbox0 %#x", mbox0);
-       KDASSERTMSG(mbox1 == 0, "mbox1 %#x", mbox1);
+               cpu->cpu_ip2_en[1] = X(CIU_IP2_EN1(cpunum));
+               cpu->cpu_ip3_en[1] = X(CIU_IP3_EN1(cpunum));
+               cpu->cpu_ip4_en[1] = X(CIU_IP4_EN1(cpunum));
 
-       sum0 = mips3_ld(int_sum0);
-       sum1 = mips3_ld(int_sum1);
+               cpu->cpu_wdog = X(CIU_WDOG(cpunum));
+               cpu->cpu_pp_poke = X(CIU_PP_POKE(cpunum));
 
-       KDASSERTMSG((sum0 & sum_mbox_lo) == 0, "sum0 %#"PRIx64, sum0);
-       KDASSERTMSG((sum0 & sum_mbox_hi) != 0, "sum0 %#"PRIx64, sum0);
-
-       KDASSERTMSG((sum1 & sum_mbox_lo) == 0, "sum1 %#"PRIx64, sum1);
-       KDASSERTMSG((sum1 & sum_mbox_hi) == 0, "sum1 %#"PRIx64, sum1);
-}
+#ifdef MULTIPROCESSOR
+               cpu->cpu_mbox_set = X(CIU_MBOX_SET(cpunum));
+               cpu->cpu_mbox_clr = X(CIU_MBOX_CLR(cpunum));
 #endif
+       }
 
 #undef X
 
+}
+
 void
 octeon_intr_init(struct cpu_info *ci)
 {
-#ifdef DIAGNOSTIC
        const int cpunum = cpu_index(ci);
-#endif
+       struct cpu_softc *cpu = &octeon_cpu_softc[cpunum];
        const char * const xname = cpu_name(ci);
-       struct cpu_softc *cpu = ci->ci_softc;
        int bank;
 
+       cpu->cpu_ci = ci;
+       ci->ci_softc = cpu;
+
+       KASSERT(cpunum == ci->ci_cpuid);
 
        if (ci->ci_cpuid == 0) {
-               KASSERT(ci->ci_softc == &octeon_cpu0_softc);
                ipl_sr_map = octeon_ipl_sr_map;
                mutex_init(&octeon_intr_lock, MUTEX_DEFAULT, IPL_HIGH);
 #ifdef MULTIPROCESSOR
                mips_locoresw.lsw_send_ipi = octeon_send_ipi;
 #endif
-#ifdef DEBUG
-               octeon_mbox_test();
-#endif
-       } else {
-               KASSERT(cpunum == 1);
-#ifdef MULTIPROCESSOR



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