Source-Changes-HG archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

[src/trunk]: src/sys/dev/pci - Allow time for the management firmware to ente...



details:   https://anonhg.NetBSD.org/src/rev/0530780d85d4
branches:  trunk
changeset: 998011:0530780d85d4
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Fri Apr 05 07:15:26 2019 +0000

description:
- Allow time for the management firmware to enter the running state.
- Enable/Disable management frames (NC-SI) to flow to the MCP if MFW exists.
- Print the boot code version, management firmware version and some flags.
- Gbps -> GT/s for PCIe speed.
- Use aprint_*() in bnx_print_adapter_info().
- Use braces for some macors' argument.
- Remove unused macros.
- KNF.

diffstat:

 sys/dev/pci/if_bnx.c    |  130 ++++++++++++++++++++++++++++++++++++++---------
 sys/dev/pci/if_bnxreg.h |   93 +++++++++++++++++++++-------------
 sys/dev/pci/if_bnxvar.h |    5 +-
 3 files changed, 164 insertions(+), 64 deletions(-)

diffs (truncated from 415 to 300 lines):

diff -r 67dbccb1ffd9 -r 0530780d85d4 sys/dev/pci/if_bnx.c
--- a/sys/dev/pci/if_bnx.c      Fri Apr 05 07:04:51 2019 +0000
+++ b/sys/dev/pci/if_bnx.c      Fri Apr 05 07:15:26 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_bnx.c,v 1.77 2019/04/05 07:04:51 msaitoh Exp $      */
+/*     $NetBSD: if_bnx.c,v 1.78 2019/04/05 07:15:26 msaitoh Exp $      */
 /*     $OpenBSD: if_bnx.c,v 1.101 2013/03/28 17:21:44 brad Exp $       */
 
 /*-
@@ -35,7 +35,7 @@
 #if 0
 __FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $");
 #endif
-__KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.77 2019/04/05 07:04:51 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.78 2019/04/05 07:15:26 msaitoh Exp $");
 
 /*
  * The following controllers are supported by this driver:
@@ -462,30 +462,46 @@
 static void
 bnx_print_adapter_info(struct bnx_softc *sc)
 {
-
-       aprint_normal_dev(sc->bnx_dev, "ASIC BCM%x %c%d %s(0x%08x)\n",
+       device_t dev = sc->bnx_dev;
+       int i = 0;
+
+       aprint_normal_dev(dev, "ASIC BCM%x %c%d %s(0x%08x)\n",
            BNXNUM(sc), 'A' + BNXREV(sc), BNXMETAL(sc),
            (BNX_CHIP_BOND_ID(sc) == BNX_CHIP_BOND_ID_SERDES_BIT)
            ? "Serdes " : "", sc->bnx_chipid);
 
        /* Bus info. */
        if (sc->bnx_flags & BNX_PCIE_FLAG) {
-               aprint_normal_dev(sc->bnx_dev, "PCIe x%d ",
-                   sc->link_width);
+               aprint_normal_dev(dev, "PCIe x%d ", sc->link_width);
                switch (sc->link_speed) {
-               case 1: aprint_normal("2.5Gbps\n"); break;
-               case 2: aprint_normal("5Gbps\n"); break;
+               case 1: aprint_normal("2.5GT/s\n"); break;
+               case 2: aprint_normal("5GT/s\n"); break;
                default: aprint_normal("Unknown link speed\n");
                }
        } else {
-               aprint_normal_dev(sc->bnx_dev, "PCI%s %dbit %dMHz\n",
+               aprint_normal_dev(dev, "PCI%s %dbit %dMHz\n",
                    ((sc->bnx_flags & BNX_PCIX_FLAG) ? "-X" : ""),
                    (sc->bnx_flags & BNX_PCI_32BIT_FLAG) ? 32 : 64,
                    sc->bus_speed_mhz);
        }
 
-       aprint_normal_dev(sc->bnx_dev,
-           "Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n",
+       /* Firmware version and device features. */
+       aprint_normal_dev(dev, "B/C (%s); Bufs (RX:%d;TX:%d); Flags (",
+           sc->bnx_bc_ver, RX_PAGES, TX_PAGES);
+
+       if (sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) {
+               if (i > 0) aprint_normal("|");
+               aprint_normal("2.5G"); i++;
+       }
+
+       if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) {
+               if (i > 0) aprint_normal("|");
+               aprint_normal("MFW); MFW (%s)\n", sc->bnx_mfw_ver);
+       } else {
+               aprint_normal(")\n");
+       }
+
+       aprint_normal_dev(dev, "Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n",
            sc->bnx_rx_quick_cons_trip_int,
            sc->bnx_rx_quick_cons_trip,
            sc->bnx_rx_ticks_int,
@@ -569,6 +585,7 @@
        int                     mii_flags = MIIF_FORCEANEG;
        pcireg_t                memtype;
        char intrbuf[PCI_INTRSTR_LEN];
+       int i, j;
 
        if (bnx_tx_pool == NULL) {
                bnx_tx_pool = malloc(sizeof(*bnx_tx_pool), M_DEVBUF, M_NOWAIT);
@@ -650,6 +667,64 @@
        sc->bnx_flags = 0;
        sc->bnx_phy_flags = 0;
 
+       /* Fetch the bootcode revision. */
+       val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_BC_REV);
+       for (i = 0, j = 0; i < 3; i++) {
+               uint8_t num;
+               int k, skip0;
+
+               num = (uint8_t)(val >> (24 - (i * 8)));
+               for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
+                       if (num >= k || !skip0 || k == 1) {
+                               sc->bnx_bc_ver[j++] = (num / k) + '0';
+                               skip0 = 0;
+                       }
+               }
+               if (i != 2)
+                       sc->bnx_bc_ver[j++] = '.';
+       }
+
+       /* Check if any management firmware is enabled. */
+       val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE);
+       if (val & BNX_PORT_FEATURE_ASF_ENABLED) {
+               DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n");
+               sc->bnx_flags |= BNX_MFW_ENABLE_FLAG;
+
+               /* Allow time for firmware to enter the running state. */
+               for (i = 0; i < 30; i++) {
+                       val = REG_RD_IND(sc, sc->bnx_shmem_base +
+                           BNX_BC_STATE_CONDITION);
+                       if (val & BNX_CONDITION_MFW_RUN_MASK)
+                               break;
+                       DELAY(10000);
+               }
+
+               /* Check if management firmware is running. */
+               val = REG_RD_IND(sc, sc->bnx_shmem_base +
+                   BNX_BC_STATE_CONDITION);
+               val &= BNX_CONDITION_MFW_RUN_MASK;
+               if ((val != BNX_CONDITION_MFW_RUN_UNKNOWN) &&
+                   (val != BNX_CONDITION_MFW_RUN_NONE)) {
+                       uint32_t addr = REG_RD_IND(sc, sc->bnx_shmem_base +
+                           BNX_MFW_VER_PTR);
+
+                       /* Read the management firmware version string. */
+                       for (j = 0; j < 3; j++) {
+                               val = bnx_reg_rd_ind(sc, addr + j * 4);
+                               val = bswap32(val);
+                               memcpy(&sc->bnx_mfw_ver[i], &val, 4);
+                               i += 4;
+                       }
+               } else {
+                       /* May cause firmware synchronization timeouts. */
+                       BNX_PRINTF(sc, "%s(%d): Management firmware enabled "
+                           "but not running!\n", __FILE__, __LINE__);
+                       strcpy(sc->bnx_mfw_ver, "NOT RUNNING!");
+
+                       /* ToDo: Any action the driver should take? */
+               }
+       }
+
        bnx_probe_pci_caps(sc);
 
        /* Get PCI bus information (speed and type). */
@@ -1548,7 +1623,7 @@
                if (val & BNX_NVM_COMMAND_DONE) {
                        val = REG_RD(sc, BNX_NVM_READ);
 
-                       val = bnx_be32toh(val);
+                       val = be32toh(val);
                        memcpy(ret_val, &val, 4);
                        break;
                }
@@ -2059,7 +2134,7 @@
        if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0)
                goto bnx_nvram_test_done;
 
-       magic = bnx_be32toh(buf[0]);
+       magic = be32toh(buf[0]);
        if (magic != BNX_NVRAM_MAGIC) {
                rc = ENODEV;
                BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! "
@@ -2841,7 +2916,7 @@
        struct cpu_reg cpu_reg;
        struct fw_info fw;
 
-       switch(BNX_CHIP_NUM(sc)) {
+       switch (BNX_CHIP_NUM(sc)) {
        case BNX_CHIP_NUM_5709:
                /* Initialize the RV2P processor. */
                if (BNX_CHIP_REV(sc) == BNX_CHIP_REV_Ax) {
@@ -3600,6 +3675,13 @@
        /* Initialize the on-boards CPUs */
        bnx_init_cpus(sc);
 
+       /* Enable management frames (NC-SI) to flow to the MCP. */
+       if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) {
+               val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) |
+                   BNX_RPM_MGMT_PKT_CTRL_MGMT_EN;
+               REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val);
+       }
+
        /* Prepare NVRAM for access. */
        if (bnx_init_nvram(sc)) {
                rc = ENODEV;
@@ -3725,19 +3807,6 @@
                goto bnx_blockinit_exit;
        }
 
-       /* Check if any management firmware is running. */
-       reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE);
-       if (reg & (BNX_PORT_FEATURE_ASF_ENABLED |
-           BNX_PORT_FEATURE_IMD_ENABLED)) {
-               DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n");
-               sc->bnx_flags |= BNX_MFW_ENABLE_FLAG;
-       }
-
-       sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base +
-           BNX_DEV_INFO_BC_REV);
-
-       DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver);
-
        /* Enable DMA */
        if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) {
                val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL);
@@ -3748,6 +3817,13 @@
        /* Allow bootcode to apply any additional fixes before enabling MAC. */
        rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET);
 
+       /* Disable management frames (NC-SI) from flowing to the MCP. */
+       if (sc->bnx_flags & BNX_MFW_ENABLE_FLAG) {
+               val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) &
+                   ~BNX_RPM_MGMT_PKT_CTRL_MGMT_EN;
+               REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val);
+       }
+
        /* Enable all remaining blocks in the MAC. */
        if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) {
                REG_WR(sc, BNX_MISC_ENABLE_SET_BITS,
diff -r 67dbccb1ffd9 -r 0530780d85d4 sys/dev/pci/if_bnxreg.h
--- a/sys/dev/pci/if_bnxreg.h   Fri Apr 05 07:04:51 2019 +0000
+++ b/sys/dev/pci/if_bnxreg.h   Fri Apr 05 07:15:26 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_bnxreg.h,v 1.23 2019/04/04 12:38:27 msaitoh Exp $   */
+/*     $NetBSD: if_bnxreg.h,v 1.24 2019/04/05 07:15:26 msaitoh Exp $   */
 /*     $OpenBSD: if_bnxreg.h,v 1.33 2009/09/05 16:02:28 claudio Exp $  */
 
 /*-
@@ -118,17 +118,17 @@
 #define BNX_VERBOSE            (BNX_CP_ALL | BNX_LEVEL_VERBOSE)
 #define BNX_EXCESSIVE          (BNX_CP_ALL | BNX_LEVEL_EXCESSIVE)
 
-#define BNX_CODE_PATH(cp)      ((cp & BNX_CP_MASK) & bnx_debug)
+#define BNX_CODE_PATH(cp)      (((cp) & BNX_CP_MASK) & bnx_debug)
 #define BNX_MSG_LEVEL(lv)      \
-    ((lv & BNX_LEVEL_MASK) <= (bnx_debug & BNX_LEVEL_MASK))
+       (((lv) & BNX_LEVEL_MASK) <= (bnx_debug & BNX_LEVEL_MASK))
 #define BNX_LOG_MSG(m)         (BNX_CODE_PATH(m) && BNX_MSG_LEVEL(m))
 
 #ifdef BNX_DEBUG
 
 /* Print a message based on the logging level and code path. */
-#define DBPRINT(sc, level, format, args...)                    \
-       if (BNX_LOG_MSG(level)) {                               \
-               aprint_debug_dev(sc->bnx_dev, format, ## args); \
+#define DBPRINT(sc, level, format, args...)                            \
+       if (BNX_LOG_MSG(level)) {                                       \
+               aprint_debug_dev((sc)->bnx_dev, format, ## args);       \
        }
 
 /* Runs a particular command based on the logging level and code path. */
@@ -160,14 +160,14 @@
 #endif
 
 /* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */
-#define DB_RANDOMFALSE(defects)               (random() > defects)
-#define DB_OR_RANDOMFALSE(defects)  || (random() > defects)
-#define DB_AND_RANDOMFALSE(defects) && (random() > defects)
+#define DB_RANDOMFALSE(defects)               (random() > (defects))
+#define DB_OR_RANDOMFALSE(defects)  || (random() > (defects))
+#define DB_AND_RANDOMFALSE(defects) && (random() > (defects))
 
 /* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */
-#define DB_RANDOMTRUE(defects)        (random() < defects)
-#define DB_OR_RANDOMTRUE(defects)   || (random() < defects)
-#define DB_AND_RANDOMTRUE(defects)  && (random() < defects)
+#define DB_RANDOMTRUE(defects)        (random() < (defects))
+#define DB_OR_RANDOMTRUE(defects)   || (random() < (defects))
+#define DB_AND_RANDOMTRUE(defects)  && (random() < (defects))
 
 #else
 
@@ -256,25 +256,6 @@
 };
 
 /****************************************************************************/
-/* Byte order conversions.                                                 */
-/****************************************************************************/
-#define betoh32(x) be32toh(x)
-#define bnx_htobe16(x) htobe16(x)
-#define bnx_htobe32(x) htobe32(x)
-#define bnx_htobe64(x) htobe64(x)
-#define bnx_htole16(x) htole16(x)
-#define bnx_htole32(x) htole32(x)
-#define bnx_htole64(x) htole64(x)
-
-#define bnx_be16toh(x) betoh16(x)
-#define bnx_be32toh(x) betoh32(x)
-#define bnx_be64toh(x) betoh64(x)
-#define bnx_le16toh(x) letoh16(x)
-#define bnx_le32toh(x) letoh32(x)
-#define bnx_le64toh(x) letoh64(x)
-
-
-/****************************************************************************/
 /* NVRAM Access                                                                    */
 /****************************************************************************/



Home | Main Index | Thread Index | Old Index