Source-Changes-HG archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

[src-draft/trunk]: src/sys/dev/usb For delays greater than 1ms use urtwn_dela...



details:   https://anonhg.NetBSD.org/src-all/rev/e6fddc71f55c
branches:  trunk
changeset: 988404:e6fddc71f55c
user:      Nathanial Sloss <nat%netbsd.org@localhost>
date:      Sat Jun 20 08:30:12 2020 +1000

description:
For delays greater than 1ms use urtwn_delay.  NFCI.

diffstat:

 sys/dev/usb/if_urtwn.c |  152 ++++++++++++++++++++++++------------------------
 1 files changed, 76 insertions(+), 76 deletions(-)

diffs (truncated from 545 to 300 lines):

diff -r 32e54525d160 -r e6fddc71f55c sys/dev/usb/if_urtwn.c
--- a/sys/dev/usb/if_urtwn.c    Sat Jun 20 08:29:05 2020 +1000
+++ b/sys/dev/usb/if_urtwn.c    Sat Jun 20 08:30:12 2020 +1000
@@ -1210,7 +1210,7 @@
        for (ntries = 0; ntries < 100; ntries++) {
                if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur)))
                        break;
-               DELAY(2000);
+               urtwn_delay_ms(sc, 2);
        }
        if (ntries == 100) {
                aprint_error_dev(sc->sc_dev,
@@ -1261,7 +1261,7 @@
 
        urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
            SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
-       DELAY(1000);
+       urtwn_delay_ms(sc, 1);
 }
 
 static void
@@ -1271,7 +1271,7 @@
 
        urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
            SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
-       DELAY(1000);
+       urtwn_delay_ms(sc, 1);
 }
 
 static void
@@ -1281,7 +1281,7 @@
 
        urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
            SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
-       DELAY(1000);
+       urtwn_delay_ms(sc, 1);
 }
 
 static uint32_t
@@ -1296,16 +1296,16 @@
 
        urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
            reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);
-       DELAY(1000);
+       urtwn_delay_ms(sc, 1);
 
        urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
            RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
            R92C_HSSI_PARAM2_READ_EDGE);
-       DELAY(1000);
+       urtwn_delay_ms(sc, 1);
 
        urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
            reg[0] | R92C_HSSI_PARAM2_READ_EDGE);
-       DELAY(1000);
+       urtwn_delay_ms(sc, 1);
 
        if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) {
                val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
@@ -2356,7 +2356,7 @@
        callout_stop(&sc->sc_scan_to);
        callout_stop(&sc->sc_calib_to);
 
-       DELAY(1000);
+       urtwn_delay_ms(sc, 1);
 
        switch (ostate) {
        case IEEE80211_S_INIT:
@@ -2413,7 +2413,7 @@
                            urtwn_read_1(sc, R92C_BCN_CTRL) &
                            ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT));
                }
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
 
                /* Reset EDCA parameters. */
                urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217);
@@ -2432,7 +2432,7 @@
                break;
        }
 
-       DELAY(1000);
+       urtwn_delay_ms(sc, 1);
 
        switch (nstate) {
        case IEEE80211_S_INIT:
@@ -2459,7 +2459,7 @@
                                urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
                        }
 
-                       DELAY(1000);
+                       urtwn_delay_ms(sc, 1);
                        /* Set media status to 'No Link'. */
                        urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK);
 
@@ -2477,7 +2477,7 @@
                              R92C_BCN_CTRL_DIS_TSF_UDT0);
                }
 
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
                /* Make link LED blink during scan. */
                urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink);
 
@@ -2503,13 +2503,13 @@
                reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
                urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
 
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
                if (!ISSET(sc->chip, URTWN_CHIP_88E)) {
                        reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
                        reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
                        urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
                }
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
 
                /* Set media status to 'No Link'. */
                urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK);
@@ -2567,7 +2567,7 @@
                        break;
                }
 
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
                /* Set media status to 'Associated'. */
                urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc));
 
@@ -2583,7 +2583,7 @@
                } else /* IEEE_MODE_11NG */
                        urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 12); /* MCS 0 */
 
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
 
                /* Enable Rx of data frames. */
                urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
@@ -4401,7 +4401,7 @@
                error = ETIMEDOUT;
                goto fail;
        }
-       DELAY(10000);
+       urtwn_delay_ms(sc, 10);
  fail:
        firmware_free(fw, fwlen);
        return error;
@@ -4671,48 +4671,48 @@
                reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);
                reg = (reg & ~0x00000003) | 0x2;
                urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
 
                reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);
                reg = (reg & ~0x00300033) | 0x00200022;
                urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
 
                reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);
                reg = (reg & ~0xff000000) | (0x45 << 24);
                urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
 
                reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
                reg = (reg & ~0x000000ff) | 0x23;
                urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
 
                reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
                reg = (reg & ~0x00000030) | (1 << 4);
                urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
 
                reg = urtwn_bb_read(sc, 0xe74);
                reg = (reg & ~0x0c000000) | (2 << 26);
                urtwn_bb_write(sc, 0xe74, reg);
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
                reg = urtwn_bb_read(sc, 0xe78);
                reg = (reg & ~0x0c000000) | (2 << 26);
                urtwn_bb_write(sc, 0xe78, reg);
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
                reg = urtwn_bb_read(sc, 0xe7c);
                reg = (reg & ~0x0c000000) | (2 << 26);
                urtwn_bb_write(sc, 0xe7c, reg);
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
                reg = urtwn_bb_read(sc, 0xe80);
                reg = (reg & ~0x0c000000) | (2 << 26);
                urtwn_bb_write(sc, 0xe80, reg);
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
                reg = urtwn_bb_read(sc, 0xe88);
                reg = (reg & ~0x0c000000) | (2 << 26);
                urtwn_bb_write(sc, 0xe88, reg);
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
        }
 
        /* Write AGC values. */
@@ -4738,7 +4738,7 @@
                urtwn_bb_write(sc, R92C_AFE_CTRL3,
                    RW(reg, R92C_AFE_XTAL_CTRL_ADDR,
                    crystalcap | crystalcap << 6));
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
                urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb);
        } else if (ISSET(sc->chip, URTWN_CHIP_88E)) {
                crystalcap = sc->r88e_rom[0xb9];
@@ -4749,14 +4749,14 @@
                urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL,
                    RW(reg, R92C_AFE_XTAL_CTRL_ADDR,
                    crystalcap | crystalcap << 6));
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
        } else {
                if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
                    R92C_HSSI_PARAM2_CCK_HIPWR) {
                        SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR);
                }
        }
-       DELAY(1000);
+       urtwn_delay_ms(sc, 1);
 }
 
 static void __noinline
@@ -4831,7 +4831,7 @@
                /* Restore RF_ENV control type. */
                reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask;
                urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved);
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
        }
 
        if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
@@ -4984,26 +4984,26 @@
                reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
                reg = RW(reg, R92C_TXAGC_A_CCK1,  power[0]);
                urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
 
                reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
                reg = RW(reg, R92C_TXAGC_A_CCK2,  power[1]);
                reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);
                reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);
                urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
        } else {
                reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
                reg = RW(reg, R92C_TXAGC_B_CCK1,  power[0]);
                reg = RW(reg, R92C_TXAGC_B_CCK2,  power[1]);
                reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);
                urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
 
                reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
                reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);
                urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
-               DELAY(1000);
+               urtwn_delay_ms(sc, 1);
        }
        /* Write per-OFDM rate Tx power. */
        urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
@@ -5011,38 +5011,38 @@
            SM(R92C_TXAGC_RATE09, power[ 5]) |
            SM(R92C_TXAGC_RATE12, power[ 6]) |
            SM(R92C_TXAGC_RATE18, power[ 7]));
-       DELAY(1000);
+       urtwn_delay_ms(sc, 1);
        urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
            SM(R92C_TXAGC_RATE24, power[ 8]) |
            SM(R92C_TXAGC_RATE36, power[ 9]) |
            SM(R92C_TXAGC_RATE48, power[10]) |
            SM(R92C_TXAGC_RATE54, power[11]));
-       DELAY(1000);
+       urtwn_delay_ms(sc, 1);
        /* Write per-MCS Tx power. */
        urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
            SM(R92C_TXAGC_MCS00,  power[12]) |
            SM(R92C_TXAGC_MCS01,  power[13]) |
            SM(R92C_TXAGC_MCS02,  power[14]) |
            SM(R92C_TXAGC_MCS03,  power[15]));
-       DELAY(1000);
+       urtwn_delay_ms(sc, 1);
        urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
            SM(R92C_TXAGC_MCS04,  power[16]) |
            SM(R92C_TXAGC_MCS05,  power[17]) |
            SM(R92C_TXAGC_MCS06,  power[18]) |
            SM(R92C_TXAGC_MCS07,  power[19]));
-       DELAY(1000);
+       urtwn_delay_ms(sc, 1);



Home | Main Index | Thread Index | Old Index