[src/trunk]: src/sys/arch/evbarm/marvell Add ARMEB support to marvell_start.

[rin <rin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/13e40ffb821b
branches:  trunk
changeset: 985536:13e40ffb821b
user:      rin <rin%NetBSD.org@localhost>
date:      Mon Aug 30 00:00:02 2021 +0000

description:
Add ARMEB support to marvell_start.

Since u-boot is running in little-endian mode, first few instructions
(to switch byte-order) should be encoded in little-endian. After that,
nop's in little-endian should appear in order to flush prefetch buffer.
Then, CPWAIT() ensure entering in big-endian mode.

diffstat:

 sys/arch/evbarm/marvell/marvell_start.S |  23 +++++++++++++++++++++--
 1 files changed, 21 insertions(+), 2 deletions(-)

diffs (44 lines):

diff -r 8502d747c01d -r 13e40ffb821b sys/arch/evbarm/marvell/marvell_start.S
--- a/sys/arch/evbarm/marvell/marvell_start.S   Sun Aug 29 23:49:32 2021 +0000
+++ b/sys/arch/evbarm/marvell/marvell_start.S   Mon Aug 30 00:00:02 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: marvell_start.S,v 1.10 2018/10/16 11:28:30 skrll Exp $ */
+/*     $NetBSD: marvell_start.S,v 1.11 2021/08/30 00:00:02 rin Exp $ */
 /*
  * Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation.
  * All rights reserved.
@@ -66,7 +66,7 @@
 #include <evbarm/marvell/marvellreg.h>
 #include "assym.h"
 
-RCSID("$NetBSD: marvell_start.S,v 1.10 2018/10/16 11:28:30 skrll Exp $")
+RCSID("$NetBSD: marvell_start.S,v 1.11 2021/08/30 00:00:02 rin Exp $")
 
 #ifndef SDRAM_START
 #define SDRAM_START    0x00000000
@@ -104,6 +104,25 @@
         *  in VA 0xc0200000..
         */
 
+#ifdef __ARMEB__
+       /*
+        * u-boot is running in little-endian mode. Therefore, we need to
+        * encode first few instructions in the opposite byte order.
+        */
+
+       /* Turn on CPU_CONTROL_BEND_ENABLE bit. */
+       .word   0x104f11ee      /* mrc p15, 0, r4, c1, c0, 0 */
+       .word   0x804084e3      /* orr r4, r4, #CPU_CONTROL_BEND_ENABLE */
+       .word   0x104f01ee      /* mcr p15, 0, r4, c1, c0, 0 */
+
+       /* Flush prefetch buffer. */
+       .word   0x0000a0e1      /* nop */
+       .word   0x0000a0e1      /* nop */
+       .word   0x0000a0e1      /* nop */
+
+       CPWAIT(r4)
+#endif
+
        /* Check cores */
        mrc     p15, 0, r4, c0, c0, 0
        and     r4, r4, #CPU_ID_CPU_MASK