[src/trunk]: src/sys/arch/arm/footbridge lower case for hex numbers.

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/a2f58ac93a19
branches:  trunk
changeset: 985429:a2f58ac93a19
user:      skrll <skrll%NetBSD.org@localhost>
date:      Tue Aug 24 08:39:50 2021 +0000

description:
lower case for hex numbers.
consistent #define<tab>
same binary before and after.

diffstat:

 sys/arch/arm/footbridge/dc21285mem.h |  52 ++++++++++++++++++------------------
 1 files changed, 26 insertions(+), 26 deletions(-)

diffs (86 lines):

diff -r 235bfde72e06 -r a2f58ac93a19 sys/arch/arm/footbridge/dc21285mem.h
--- a/sys/arch/arm/footbridge/dc21285mem.h      Tue Aug 24 07:32:31 2021 +0000
+++ b/sys/arch/arm/footbridge/dc21285mem.h      Tue Aug 24 08:39:50 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: dc21285mem.h,v 1.2 2001/06/09 10:44:11 chris Exp $     */
+/*     $NetBSD: dc21285mem.h,v 1.3 2021/08/24 08:39:50 skrll Exp $     */
 
 /*
  * Copyright (c) 1997,1998 Mark Brinicombe.
@@ -39,51 +39,51 @@
  */
 
 #define        DC21285_SDRAM_BASE              0x00000000
-#define DC21285_SDRAM_SIZE             0x10000000      /* 256 MB */
+#define        DC21285_SDRAM_SIZE              0x10000000      /* 256 MB */
 
 #define        DC21285_SDRAM_A0MR              0x40000000
 #define        DC21285_SDRAM_A1MR              0x40004000
 #define        DC21285_SDRAM_A2MR              0x40008000
-#define        DC21285_SDRAM_A3MR              0x4000C000
+#define        DC21285_SDRAM_A3MR              0x4000c000
 
 #define        DC21285_XBUS_XCS0               0x40010000
 #define        DC21285_XBUS_XCS1               0x40011000
 #define        DC21285_XBUS_XCS2               0x40012000
 #define        DC21285_XBUS_NOCS               0x40013000
 
-#define DC21285_ROM_BASE               0x41000000
-#define DC21285_ROM_SIZE               0x01000000      /* 16MB */
+#define        DC21285_ROM_BASE                0x41000000
+#define        DC21285_ROM_SIZE                0x01000000      /* 16MB */
 
-#define DC21285_ARMCSR_BASE            0x42000000
-#define DC21285_ARMCSR_SIZE            0x00100000      /* 1MB */
+#define        DC21285_ARMCSR_BASE             0x42000000
+#define        DC21285_ARMCSR_SIZE             0x00100000      /* 1MB */
 
-#define DC21285_SA_CACHE_FLUSH_BASE    0x50000000
-#define DC21285_SA_CACHE_FLUSH_SIZE    0x01000000      /* 16MB */
+#define        DC21285_SA_CACHE_FLUSH_BASE     0x50000000
+#define        DC21285_SA_CACHE_FLUSH_SIZE     0x01000000      /* 16MB */
 
-#define DC21285_OUTBOUND_WRITE_FLUSH   0x78000000
+#define        DC21285_OUTBOUND_WRITE_FLUSH    0x78000000
 
-#define DC21285_PCI_IACK_SPECIAL       0x79000000
-#define DC21285_PCI_TYPE_1_CONFIG      0x7A000000
-#define DC21285_PCI_TYPE_0_CONFIG      0x7B000000
-#define DC21285_PCI_IO_BASE            0x7C000000
-#define DC21285_PCI_IO_SIZE            0x00010000      /* 64K */
-#define DC21285_PCI_MEM_BASE           0x80000000
-#define DC21285_PCI_MEM_SIZE           0x80000000      /* 2GB */
+#define        DC21285_PCI_IACK_SPECIAL        0x79000000
+#define        DC21285_PCI_TYPE_1_CONFIG       0x7a000000
+#define        DC21285_PCI_TYPE_0_CONFIG       0x7b000000
+#define        DC21285_PCI_IO_BASE             0x7c000000
+#define        DC21285_PCI_IO_SIZE             0x00010000      /* 64K */
+#define        DC21285_PCI_MEM_BASE            0x80000000
+#define        DC21285_PCI_MEM_SIZE            0x80000000      /* 2GB */
 
 /*
  * Standard Virtual memory map used for the DC21285 'Footbridge'
  */
-#define DC21285_ARMCSR_VBASE           0xFD000000
-#define        DC21285_ARMCSR_VSIZE            0x00100000      /* 1MB */
-#define        DC21285_CACHE_FLUSH_VBASE       0xFD100000
+#define        DC21285_ARMCSR_VBASE            0xfd000000
+#define        DC21285_ARMCSR_VSIZE            0x00100000      /* 1mB */
+#define        DC21285_CACHE_FLUSH_VBASE       0xfd100000
 #define        DC21285_CACHE_FLUSH_VSIZE       0x00100000      /* 1MB */
-#define        DC21285_PCI_IO_VBASE            0xFD200000
-#define        DC21285_PCI_IO_VSIZE            0x00100000      /* 1MB */
-#define        DC21285_PCI_IACK_VBASE          0xFD300000
+#define        DC21285_PCI_IO_VBASE            0xfd200000
+#define        DC21285_PCI_IO_VSIZE            0x00100000      /* 1mB */
+#define        DC21285_PCI_IACK_VBASE          0xfd300000
 #define        DC21285_PCI_IACK_VSIZE          0x00100000      /* 1MB */
-#define        DC21285_PCI_ISA_MEM_VBASE       0xFD400000
+#define        DC21285_PCI_ISA_MEM_VBASE       0xfd400000
 #define        DC21285_PCI_ISA_MEM_VSIZE       0x00100000      /* 1MB */
-#define        DC21285_PCI_TYPE_1_CONFIG_VBASE 0xFE000000
+#define        DC21285_PCI_TYPE_1_CONFIG_VBASE 0xfe000000
 #define        DC21285_PCI_TYPE_1_CONFIG_VSIZE 0x01000000      /* 16MB */
-#define        DC21285_PCI_TYPE_0_CONFIG_VBASE 0xFF000000
+#define        DC21285_PCI_TYPE_0_CONFIG_VBASE 0xff000000
 #define        DC21285_PCI_TYPE_0_CONFIG_VSIZE 0x01000000      /* 16MB */