[src/trunk]: src/sys/arch/mips/cavium Initialize PageMask and Wired registers...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/cec247677c3b
branches:  trunk
changeset: 974071:cec247677c3b
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Wed Jul 22 15:01:18 2020 +0000

description:
Initialize PageMask and Wired registers on secondary processors.

diffstat:

 sys/arch/mips/cavium/octeon_cpunode.c |  9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletions(-)

diffs (35 lines):

diff -r 655d21b27288 -r cec247677c3b sys/arch/mips/cavium/octeon_cpunode.c
--- a/sys/arch/mips/cavium/octeon_cpunode.c     Wed Jul 22 15:00:49 2020 +0000
+++ b/sys/arch/mips/cavium/octeon_cpunode.c     Wed Jul 22 15:01:18 2020 +0000
@@ -29,7 +29,7 @@
 #define __INTR_PRIVATE
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(0, "$NetBSD: octeon_cpunode.c,v 1.16 2020/07/21 06:01:10 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_cpunode.c,v 1.17 2020/07/22 15:01:18 jmcneill Exp $");
 
 #include "locators.h"
 #include "cpunode.h"
@@ -51,6 +51,7 @@
 #include <mips/cache.h>
 #include <mips/mips_opcode.h>
 #include <mips/mips3_clock.h>
+#include <mips/mips3_pte.h>
 
 #include <mips/cavium/octeonvar.h>
 #include <mips/cavium/dev/octeon_ciureg.h>
@@ -204,8 +205,14 @@
 static void
 octeon_cpu_init(struct cpu_info *ci)
 {
+       extern const mips_locore_jumpvec_t mips64r2_locore_vec;
        bool ok __diagused;
 
+       mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_TO_MASK(PAGE_SIZE));
+       mips3_cp0_wired_write(0);
+       (*mips64r2_locore_vec.ljv_tlb_invalidate_all)();
+       mips3_cp0_wired_write(pmap_tlb0_info.ti_wired);
+
        // First thing is setup the execption vectors for this cpu.
        mips64r2_vector_init(&mips_splsw);