Source-Changes-HG archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

[src/trunk]: src/sys/dev/ic Mask all the MMC counter interrupts if the MMC mo...



details:   https://anonhg.NetBSD.org/src/rev/e2a57873ed6e
branches:  trunk
changeset: 972170:e2a57873ed6e
user:      chs <chs%NetBSD.org@localhost>
date:      Sun May 17 21:50:47 2020 +0000

description:
Mask all the MMC counter interrupts if the MMC module is present.

diffstat:

 sys/dev/ic/dwc_gmac.c     |  14 +++++++++++-
 sys/dev/ic/dwc_gmac_reg.h |  51 +++++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 61 insertions(+), 4 deletions(-)

diffs (121 lines):

diff -r 2335749e7b5e -r e2a57873ed6e sys/dev/ic/dwc_gmac.c
--- a/sys/dev/ic/dwc_gmac.c     Sun May 17 20:29:39 2020 +0000
+++ b/sys/dev/ic/dwc_gmac.c     Sun May 17 21:50:47 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_gmac.c,v 1.69 2020/01/29 14:14:55 thorpej Exp $ */
+/* $NetBSD: dwc_gmac.c,v 1.70 2020/05/17 21:50:47 chs Exp $ */
 
 /*-
  * Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
@@ -41,7 +41,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: dwc_gmac.c,v 1.69 2020/01/29 14:14:55 thorpej Exp $");
+__KERNEL_RCSID(1, "$NetBSD: dwc_gmac.c,v 1.70 2020/05/17 21:50:47 chs Exp $");
 
 /* #define     DWC_GMAC_DEBUG  1 */
 
@@ -254,6 +254,16 @@
        } else {
                sc->sc_descm = &desc_methods_standard;
        }
+       if (hwft & GMAC_DMA_FEAT_RMON) {
+               uint32_t val;
+
+               /* Mask all MMC interrupts */
+               val = 0xffffffff;
+               bus_space_write_4(sc->sc_bst, sc->sc_bsh,
+                   GMAC_MMC_RX_INT_MSK, val);
+               bus_space_write_4(sc->sc_bst, sc->sc_bsh,
+                   GMAC_MMC_TX_INT_MSK, val);
+       }
 
        /*
         * Allocate Tx and Rx rings
diff -r 2335749e7b5e -r e2a57873ed6e sys/dev/ic/dwc_gmac_reg.h
--- a/sys/dev/ic/dwc_gmac_reg.h Sun May 17 20:29:39 2020 +0000
+++ b/sys/dev/ic/dwc_gmac_reg.h Sun May 17 21:50:47 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_gmac_reg.h,v 1.19 2018/10/08 17:09:31 martin Exp $ */
+/* $NetBSD: dwc_gmac_reg.h,v 1.20 2020/05/17 21:50:47 chs Exp $ */
 
 /*-
  * Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
@@ -79,6 +79,46 @@
 #define        AWIN_GMAC_MAC_FLOWCTRL_TFE      __BIT(1)
 #define        AWIN_GMAC_MAC_FLOWCTRL_BUSY     __BIT(0)
 
+#define        GMAC_MMC_CTRL                   0x0100  /* MMC control */
+#define        GMAC_MMC_RX_INTR                0x0104  /* MMC RX interrupt */
+#define        GMAC_MMC_TX_INTR                0x0108  /* MMC TX interrupt */
+#define        GMAC_MMC_RX_INT_MSK             0x010c  /* MMC RX interrupt mask */
+#define        GMAC_MMC_TX_INT_MSK             0x0110  /* MMC TX interrupt mask */
+#define        GMAC_MMC_TXOCTETCNT_GB          0x0114  /* TX octet good+bad */
+#define        GMAC_MMC_TXFRMCNT_GB            0x0118  /* TX frame good+bad */
+#define        GMAC_MMC_TXUNDFLWERR            0x0148  /* TX underflow */
+#define        GMAC_MMC_TXCARERR               0x0160  /* TX carrier error */
+#define        GMAC_MMC_TXOCTETCNT_G           0x0164  /* TX octet good */
+#define        GMAC_MMC_TXFRMCNT_G             0x0168  /* TX frame good */
+#define        GMAC_MMC_RXFRMCNT_GB            0x0180  /* RX frame good+bad */
+#define        GMAC_MMC_RXOCTETCNT_GB          0x0184  /* RX octet good+bad */
+#define        GMAC_MMC_RXOCTETCNT_G           0x0188  /* RX octet good */
+#define        GMAC_MMC_RXMCFRMCNT_G           0x0190  /* RX mcast frame good */
+#define        GMAC_MMC_RXCRCERR               0x0194  /* RX CRC error */
+#define        GMAC_MMC_RXLENERR               0x01c8  /* RX length error */
+#define        GMAC_MMC_RXFIFOOVRFLW           0x01d4  /* RX FIFO overflow */
+#define        GMAC_MMC_IPC_INT_MSK            0x0200  /* RX csum offload intr mask */
+#define        GMAC_MMC_IPC_INTR               0x0208  /* RX csum offload interrupt */
+#define        GMAC_MMC_RXIPV4GFRM             0x0210  /* RX IPv4 good frame */
+#define        GMAC_MMC_RXIPV4HDERRFRM         0x0214  /* RX IPv4 header error */
+#define        GMAC_MMC_RXIPV6GFRM             0x0224  /* RX IPv6 good frame */
+#define        GMAC_MMC_RXIPV6HDERRFRM         0x0228  /* RX IPv6 header error */
+#define        GMAC_MMC_RXUDPERRFRM            0x0234  /* RX UDP csum error frame */
+#define        GMAC_MMC_RXTCPERRFRM            0x023c  /* RX TCP csum error frame */
+#define        GMAC_MMC_RXICMPERRFRM           0x0244  /* RX ICMP csum error frame */
+#define        GMAC_MMC_RXIPV4HDERROCT         0x0254  /* RX IPv4 header error octets */
+#define        GMAC_MMC_RXIPV6HDERROCT         0x0268  /* RX IPv6 header error octets */
+#define        GMAC_MMC_RXUDPERROCT            0x0274  /* RX UDP error octets */
+#define        GMAC_MMC_RXTCPERROCT            0x027c  /* RX TCP error octets */
+#define        GMAC_MMC_RXICMPERROCT           0x0280  /* RX ICMP error octets */
+
+#define        GMAC_MMC_CTRL_FHP               __BIT(5) /* Full-Half preset */
+#define        GMAC_MMC_CTRL_CP                __BIT(4) /* Counters preset */
+#define        GMAC_MMC_CTRL_MCF               __BIT(3) /* MMC counter freeze */
+#define        GMAC_MMC_CTRL_ROR               __BIT(2) /* reset on read */
+#define        GMAC_MMC_CTRL_CSR               __BIT(1) /* Counter stop rollover */
+#define        GMAC_MMC_CTRL_CR                __BIT(0) /* Counters reset */
+
 #define        AWIN_GMAC_DMA_BUSMODE           0x1000
 #define        AWIN_GMAC_DMA_TXPOLL            0x1004
 #define        AWIN_GMAC_DMA_RXPOLL            0x1008
@@ -128,7 +168,12 @@
                                                        burst len */
 #define        GMAC_BUSMODE_RESET              __BIT(0)
 
-#define        AWIN_GMAC_MII_IRQ               __BIT(0)
+#define        AWIN_GMAC_MRCOIS                __BIT(7) /* MMC RX csum offload intr */
+#define        AWIN_GMAC_MTIS                  __BIT(6) /* MMC TX interrupt */
+#define        AWIN_GMAC_MRIS                  __BIT(3) /* MMC RX interrupt */
+#define        AWIN_GMAC_MIS                   __BIT(4) /* MMC interrupt */
+#define        AWIN_GMAC_PIS                   __BIT(3) /* PMT interrupt */
+#define        AWIN_GMAC_MII_IRQ               __BIT(0) /* RGMII interrupt */
 
 
 #define        GMAC_DMA_OP_DISABLECSDROP       __BIT(26) /* disable dropping of
@@ -146,6 +191,7 @@
 #define        GMAC_DMA_OP_RTC                 __BITS(4,3) /* RX thres control */
 #define        GMAC_DMA_OP_RXSTART             __BIT(1)  /* start RX DMA engine */
 
+#define        GMAC_DMA_INT_MMC                __BIT(27) /* MMC interrupt */
 #define        GMAC_DMA_INT_NIE                __BIT(16) /* Normal/Summary */
 #define        GMAC_DMA_INT_AIE                __BIT(15) /* Abnormal/Summary */
 #define        GMAC_DMA_INT_ERE                __BIT(14) /* Early receive */
@@ -165,6 +211,7 @@
 #define        GMAC_DMA_INT_MASK       __BITS(0,16)      /* all possible intr bits */
 
 #define GMAC_DMA_FEAT_ENHANCED_DESC    __BIT(24)
+#define GMAC_DMA_FEAT_RMON             __BIT(11) /* MMC */
 
 struct dwc_gmac_dev_dmadesc {
        uint32_t ddesc_status0;         /* Status / TDES0 */



Home | Main Index | Thread Index | Old Index