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[src/trunk]: src/sys/dev/pci Reduce diff against OpenBSD. No functional change.
details: https://anonhg.NetBSD.org/src/rev/706fbe571a37
branches: trunk
changeset: 968269:706fbe571a37
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Thu Jan 09 10:54:16 2020 +0000
description:
Reduce diff against OpenBSD. No functional change.
- USE CSR_{READ,WRITE}_*() macro.
- Move some macros from if_stge.c to if_stgereg.h
diffstat:
sys/dev/pci/if_stge.c | 188 ++++++++++++++++++----------------------------
sys/dev/pci/if_stgereg.h | 38 +++++++++-
2 files changed, 111 insertions(+), 115 deletions(-)
diffs (truncated from 533 to 300 lines):
diff -r 801694e15dd3 -r 706fbe571a37 sys/dev/pci/if_stge.c
--- a/sys/dev/pci/if_stge.c Thu Jan 09 10:46:31 2020 +0000
+++ b/sys/dev/pci/if_stge.c Thu Jan 09 10:54:16 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_stge.c,v 1.75 2019/12/26 15:32:37 msaitoh Exp $ */
+/* $NetBSD: if_stge.c,v 1.76 2020/01/09 10:54:16 msaitoh Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.75 2019/12/26 15:32:37 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.76 2020/01/09 10:54:16 msaitoh Exp $");
#include <sys/param.h>
@@ -76,23 +76,6 @@
#define STGE_VLAN_UNTAG 1
/* #define STGE_VLAN_CFI 1 */
-#define STGE_CDOFF(x) offsetof(struct stge_control_data, x)
-#define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)])
-#define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)])
-
-#define STGE_RXCHAIN_RESET(sc) \
-do { \
- (sc)->sc_rxtailp = &(sc)->sc_rxhead; \
- *(sc)->sc_rxtailp = NULL; \
- (sc)->sc_rxlen = 0; \
-} while (/*CONSTCOND*/0)
-
-#define STGE_RXCHAIN_LINK(sc, m) \
-do { \
- *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \
- (sc)->sc_rxtailp = &(m)->m_next; \
-} while (/*CONSTCOND*/0)
-
#ifdef STGE_EVENT_COUNTERS
#define STGE_EVCNT_INCR(ev) (ev)->ev_count++
#else
@@ -129,8 +112,6 @@
STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \
} while (/*CONSTCOND*/0)
-#define STGE_TIMEOUT 1000
-
static void stge_start(struct ifnet *);
static void stge_watchdog(struct ifnet *);
static int stge_ioctl(struct ifnet *, u_long, void *);
@@ -403,8 +384,7 @@
* Determine if we're copper or fiber. It affects how we
* reset the card.
*/
- if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) &
- AC_PhyMedia)
+ if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
sc->sc_usefiber = 1;
else
sc->sc_usefiber = 0;
@@ -422,18 +402,12 @@
* from EEPROM.
*/
if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) {
- enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh,
- STGE_StationAddress0) & 0xff;
- enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh,
- STGE_StationAddress0) >> 8;
- enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh,
- STGE_StationAddress1) & 0xff;
- enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh,
- STGE_StationAddress1) >> 8;
- enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh,
- STGE_StationAddress2) & 0xff;
- enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh,
- STGE_StationAddress2) >> 8;
+ enaddr[0] = CSR_READ_2(sc, STGE_StationAddress0) & 0xff;
+ enaddr[1] = CSR_READ_2(sc, STGE_StationAddress0) >> 8;
+ enaddr[2] = CSR_READ_2(sc, STGE_StationAddress1) & 0xff;
+ enaddr[3] = CSR_READ_2(sc, STGE_StationAddress1) >> 8;
+ enaddr[4] = CSR_READ_2(sc, STGE_StationAddress2) & 0xff;
+ enaddr[5] = CSR_READ_2(sc, STGE_StationAddress2) >> 8;
sc->sc_stge1023 = 0;
} else {
data = prop_dictionary_get(device_properties(self),
@@ -466,8 +440,8 @@
/*
* Read some important bits from the PhyCtrl register.
*/
- sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh,
- STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
+ sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
+ (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
/*
* Initialize our media structures and probe the MII.
@@ -643,8 +617,7 @@
for (i = 0; i < STGE_TIMEOUT; i++) {
delay(2);
- if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) &
- DMAC_TxDMAInProg) == 0)
+ if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
break;
}
@@ -836,7 +809,7 @@
/*
* Kick the transmit DMA logic.
*/
- bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl,
+ CSR_WRITE_4(sc, STGE_DMACtrl,
sc->sc_DMACtrl | DMAC_TxDMAPollNow);
/*
@@ -946,12 +919,11 @@
int wantinit;
uint16_t isr;
- if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) &
- IS_InterruptStatus) == 0)
+ if ((CSR_READ_2(sc, STGE_IntStatus) & IS_InterruptStatus) == 0)
return (0);
for (wantinit = 0; wantinit == 0;) {
- isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck);
+ isr = CSR_READ_2(sc, STGE_IntStatusAck);
if ((isr & sc->sc_IntEnable) == 0)
break;
@@ -995,8 +967,7 @@
if (isr & IS_TxComplete) {
STGE_EVCNT_INCR(&sc->sc_ev_txindintr);
for (;;) {
- txstat = bus_space_read_4(sc->sc_st, sc->sc_sh,
- STGE_TxStatus);
+ txstat = CSR_READ_4(sc, STGE_TxStatus);
if ((txstat & TS_TxComplete) == 0)
break;
if (txstat & TS_TxUnderrun) {
@@ -1020,8 +991,7 @@
if (wantinit)
stge_init(ifp);
- bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable,
- sc->sc_IntEnable);
+ CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
/* Try to get more packets going. */
if_schedule_deferred_start(ifp);
@@ -1291,29 +1261,27 @@
stge_stats_update(struct stge_softc *sc)
{
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
- bus_space_tag_t st = sc->sc_st;
- bus_space_handle_t sh = sc->sc_sh;
- (void) bus_space_read_4(st, sh, STGE_OctetRcvOk);
+ (void) CSR_READ_4(sc, STGE_OctetRcvOk);
- (void) bus_space_read_4(st, sh, STGE_FramesRcvdOk);
+ (void) CSR_READ_4(sc, STGE_FramesRcvdOk);
ifp->if_ierrors +=
- (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors);
+ (u_int) CSR_READ_2(sc, STGE_FramesLostRxErrors);
- (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk);
+ (void) CSR_READ_4(sc, STGE_OctetXmtdOk);
ifp->if_opackets +=
- bus_space_read_4(st, sh, STGE_FramesXmtdOk);
+ CSR_READ_4(sc, STGE_FramesXmtdOk);
ifp->if_collisions +=
- bus_space_read_4(st, sh, STGE_LateCollisions) +
- bus_space_read_4(st, sh, STGE_MultiColFrames) +
- bus_space_read_4(st, sh, STGE_SingleColFrames);
+ CSR_READ_4(sc, STGE_LateCollisions) +
+ CSR_READ_4(sc, STGE_MultiColFrames) +
+ CSR_READ_4(sc, STGE_SingleColFrames);
ifp->if_oerrors +=
- (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) +
- (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal);
+ (u_int) CSR_READ_2(sc, STGE_FramesAbortXSColls) +
+ (u_int) CSR_READ_2(sc, STGE_FramesWEXDeferal);
}
/*
@@ -1327,14 +1295,14 @@
uint32_t ac;
int i;
- ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl);
+ ac = CSR_READ_4(sc, STGE_AsicCtrl);
/*
* Only assert RstOut if we're fiber. We need GMII clocks
* to be present in order for the reset to complete on fiber
* cards.
*/
- bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl,
+ CSR_WRITE_4(sc, STGE_AsicCtrl,
ac | AC_GlobalReset | AC_RxReset | AC_TxReset |
AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
(sc->sc_usefiber ? AC_RstOut : 0));
@@ -1343,8 +1311,7 @@
for (i = 0; i < STGE_TIMEOUT; i++) {
delay(5000);
- if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) &
- AC_ResetBusy) == 0)
+ if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
break;
}
@@ -1364,8 +1331,6 @@
stge_init(struct ifnet *ifp)
{
struct stge_softc *sc = ifp->if_softc;
- bus_space_tag_t st = sc->sc_st;
- bus_space_handle_t sh = sc->sc_sh;
struct stge_descsoft *ds;
int i, error = 0;
@@ -1419,15 +1384,15 @@
/* Set the station address. */
for (i = 0; i < 6; i++)
- bus_space_write_1(st, sh, STGE_StationAddress0 + i,
+ CSR_WRITE_1(sc, STGE_StationAddress0 + i,
CLLADDR(ifp->if_sadl)[i]);
/*
* Set the statistics masks. Disable all the RMON stats,
* and disable selected stats in the non-RMON stats registers.
*/
- bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff);
- bus_space_write_4(st, sh, STGE_StatisticsMask,
+ CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
+ CSR_WRITE_4(sc, STGE_StatisticsMask,
(1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
(1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
(1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
@@ -1439,12 +1404,12 @@
/*
* Give the transmit and receive ring to the chip.
*/
- bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */
- bus_space_write_4(st, sh, STGE_TFDListPtrLo,
+ CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */
+ CSR_WRITE_4(sc, STGE_TFDListPtrLo,
STGE_CDTXADDR(sc, sc->sc_txdirty));
- bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */
- bus_space_write_4(st, sh, STGE_RFDListPtrLo,
+ CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */
+ CSR_WRITE_4(sc, STGE_RFDListPtrLo,
STGE_CDRXADDR(sc, sc->sc_rxptr));
/*
@@ -1452,24 +1417,24 @@
* large (255 is the max, but we use 127) -- we explicitly kick the
* transmit engine when there's actually a packet.
*/
- bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127);
+ CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
/* ..and the Rx auto-poll period. */
- bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64);
+ CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 64);
/* Initialize the Tx start threshold. */
- bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh);
+ CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
/* RX DMA thresholds, from linux */
- bus_space_write_1(st, sh, STGE_RxDMABurstThresh, 0x30);
- bus_space_write_1(st, sh, STGE_RxDMAUrgentThresh, 0x30);
+ CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
+ CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
/* Rx early threhold, from Linux */
- bus_space_write_2(st, sh, STGE_RxEarlyThresh, 0x7ff);
+ CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
/* Tx DMA thresholds, from Linux */
- bus_space_write_1(st, sh, STGE_TxDMABurstThresh, 0x30);
- bus_space_write_1(st, sh, STGE_TxDMAUrgentThresh, 0x04);
+ CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
+ CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
/*
* Initialize the Rx DMA interrupt control register. We
@@ -1478,7 +1443,7 @@
* interrupts pending reaches 8, we stop deferring the
* interrupt, and signal it immediately.
*/
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