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[src/trunk]: src/sys/arch/aarch64/include Move the TCR and TTBR defines into ...



details:   https://anonhg.NetBSD.org/src/rev/1cb22ef02cf2
branches:  trunk
changeset: 965290:1cb22ef02cf2
user:      skrll <skrll%NetBSD.org@localhost>
date:      Wed Sep 11 18:19:35 2019 +0000

description:
Move the TCR and TTBR defines into armreg.h where they below.  NFCI.

diffstat:

 sys/arch/aarch64/include/armreg.h |  60 +++++++++++++++++++++++++++++++++++-
 sys/arch/aarch64/include/pte.h    |  63 +--------------------------------------
 2 files changed, 59 insertions(+), 64 deletions(-)

diffs (160 lines):

diff -r 949468e06306 -r 1cb22ef02cf2 sys/arch/aarch64/include/armreg.h
--- a/sys/arch/aarch64/include/armreg.h Wed Sep 11 17:02:53 2019 +0000
+++ b/sys/arch/aarch64/include/armreg.h Wed Sep 11 18:19:35 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.26 2019/08/12 23:31:48 jmcneill Exp $ */
+/* $NetBSD: armreg.h,v 1.27 2019/09/11 18:19:35 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -646,7 +646,60 @@
 AARCH64REG_READ_INLINE(tcr_el1)                // Translation Control Register
 AARCH64REG_WRITE_INLINE(tcr_el1)
 
-#define TCR_PAGE_SIZE1(tcr)    (1L << ((1L << __SHIFTOUT(tcr, TCR_TG1)) + 8))
+
+/* TCR_EL1 - Translation Control Register */
+#define TCR_TBI1               __BIT(38)               /* ignore Top Byte TTBR1_EL1 */
+#define TCR_TBI0               __BIT(37)               /* ignore Top Byte TTBR0_EL1 */
+#define TCR_AS64K              __BIT(36)               /* Use 64K ASIDs */
+#define TCR_IPS                        __BITS(34,32)           /* Intermediate PhysAdr Size */
+#define  TCR_IPS_4PB           __SHIFTIN(6,TCR_IPS)    /* 52 bits (  4 PB) */
+#define  TCR_IPS_256TB         __SHIFTIN(5,TCR_IPS)    /* 48 bits (256 TB) */
+#define  TCR_IPS_16TB          __SHIFTIN(4,TCR_IPS)    /* 44 bits  (16 TB) */
+#define  TCR_IPS_4TB           __SHIFTIN(3,TCR_IPS)    /* 42 bits  ( 4 TB) */
+#define  TCR_IPS_1TB           __SHIFTIN(2,TCR_IPS)    /* 40 bits  ( 1 TB) */
+#define  TCR_IPS_64GB          __SHIFTIN(1,TCR_IPS)    /* 36 bits  (64 GB) */
+#define  TCR_IPS_4GB           __SHIFTIN(0,TCR_IPS)    /* 32 bits   (4 GB) */
+#define TCR_TG1                        __BITS(31,30)           /* TTBR1 Page Granule Size */
+#define  TCR_TG1_16KB          __SHIFTIN(1,TCR_TG1)    /* 16KB page size */
+#define  TCR_TG1_4KB           __SHIFTIN(2,TCR_TG1)    /* 4KB page size */
+#define  TCR_TG1_64KB          __SHIFTIN(3,TCR_TG1)    /* 64KB page size */
+#define TCR_SH1                        __BITS(29,28)
+#define  TCR_SH1_NONE          __SHIFTIN(0,TCR_SH1)
+#define  TCR_SH1_OUTER         __SHIFTIN(2,TCR_SH1)
+#define  TCR_SH1_INNER         __SHIFTIN(3,TCR_SH1)
+#define TCR_ORGN1              __BITS(27,26)           /* TTBR1 Outer cacheability */
+#define  TCR_ORGN1_NC          __SHIFTIN(0,TCR_ORGN1)  /* Non Cacheable */
+#define  TCR_ORGN1_WB_WA       __SHIFTIN(1,TCR_ORGN1)  /* WriteBack WriteAllocate */
+#define  TCR_ORGN1_WT          __SHIFTIN(2,TCR_ORGN1)  /* WriteThrough */
+#define  TCR_ORGN1_WB          __SHIFTIN(3,TCR_ORGN1)  /* WriteBack */
+#define TCR_IRGN1              __BITS(25,24)           /* TTBR1 Inner cacheability */
+#define  TCR_IRGN1_NC          __SHIFTIN(0,TCR_IRGN1)  /* Non Cacheable */
+#define  TCR_IRGN1_WB_WA       __SHIFTIN(1,TCR_IRGN1)  /* WriteBack WriteAllocate */
+#define  TCR_IRGN1_WT          __SHIFTIN(2,TCR_IRGN1)  /* WriteThrough */
+#define  TCR_IRGN1_WB          __SHIFTIN(3,TCR_IRGN1)  /* WriteBack */
+#define TCR_EPD1               __BIT(23)               /* Walk Disable for TTBR1_EL1 */
+#define TCR_A1                 __BIT(22)               /* ASID is in TTBR1_EL1 */
+#define TCR_T1SZ               __BITS(21,16)           /* Size offset for TTBR1_EL1 */
+#define TCR_TG0                        __BITS(15,14)           /* TTBR0 Page Granule Size */
+#define  TCR_TG0_4KB           __SHIFTIN(0,TCR_TG0)    /* 4KB page size */
+#define  TCR_TG0_64KB          __SHIFTIN(1,TCR_TG0)    /* 64KB page size */
+#define  TCR_TG0_16KB          __SHIFTIN(2,TCR_TG0)    /* 16KB page size */
+#define TCR_SH0                        __BITS(13,12)
+#define  TCR_SH0_NONE          __SHIFTIN(0,TCR_SH0)
+#define  TCR_SH0_OUTER         __SHIFTIN(2,TCR_SH0)
+#define  TCR_SH0_INNER         __SHIFTIN(3,TCR_SH0)
+#define TCR_ORGN0              __BITS(11,10)           /* TTBR0 Outer cacheability */
+#define  TCR_ORGN0_NC          __SHIFTIN(0,TCR_ORGN0)  /* Non Cacheable */
+#define  TCR_ORGN0_WB_WA       __SHIFTIN(1,TCR_ORGN0)  /* WriteBack WriteAllocate */
+#define  TCR_ORGN0_WT          __SHIFTIN(2,TCR_ORGN0)  /* WriteThrough */
+#define  TCR_ORGN0_WB          __SHIFTIN(3,TCR_ORGN0)  /* WriteBack */
+#define TCR_IRGN0              __BITS(9,8)             /* TTBR0 Inner cacheability */
+#define  TCR_IRGN0_NC          __SHIFTIN(0,TCR_IRGN0)  /* Non Cacheable */
+#define  TCR_IRGN0_WB_WA       __SHIFTIN(1,TCR_IRGN0)  /* WriteBack WriteAllocate */
+#define  TCR_IRGN0_WT          __SHIFTIN(2,TCR_IRGN0)  /* WriteThrough */
+#define  TCR_IRGN0_WB          __SHIFTIN(3,TCR_IRGN0)  /* WriteBack */
+#define TCR_EPD0               __BIT(7)                /* Walk Disable for TTBR0 */
+#define TCR_T0SZ               __BITS(5,0)             /* Size offset for TTBR0_EL1 */
 
 AARCH64REG_READ_INLINE(tpidr_el1)      // Thread ID Register (EL1)
 AARCH64REG_WRITE_INLINE(tpidr_el1)
@@ -659,6 +712,9 @@
 AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1
 AARCH64REG_WRITE_INLINE(ttbr1_el1)
 
+#define TTBR_ASID              __BITS(63,48)
+#define TTBR_BADDR             __BITS(47,0)
+
 AARCH64REG_READ_INLINE(vbar_el1)       // Vector Base Address Register
 AARCH64REG_WRITE_INLINE(vbar_el1)
 
diff -r 949468e06306 -r 1cb22ef02cf2 sys/arch/aarch64/include/pte.h
--- a/sys/arch/aarch64/include/pte.h    Wed Sep 11 17:02:53 2019 +0000
+++ b/sys/arch/aarch64/include/pte.h    Wed Sep 11 18:19:35 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.8 2019/09/11 11:43:15 jmcneill Exp $ */
+/* $NetBSD: pte.h,v 1.9 2019/09/11 18:19:35 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -128,69 +128,8 @@
 #define Ln_ENTRIES             (1 << Ln_ENTRIES_SHIFT)
 #define Ln_TABLE_SIZE          (8 << Ln_ENTRIES_SHIFT)
 
-
-/* TCR_EL1 - Translation Control Register */
-#define TCR_TBI1               __BIT(38)               /* ignore Top Byte TTBR1_EL1 */
-#define TCR_TBI0               __BIT(37)               /* ignore Top Byte TTBR0_EL1 */
-#define TCR_AS64K              __BIT(36)               /* Use 64K ASIDs */
-#define TCR_IPS                        __BITS(34,32)           /* Intermediate PhysAdr Size */
-#define  TCR_IPS_4PB           __SHIFTIN(6,TCR_IPS)    /* 52 bits (  4 PB) */
-#define  TCR_IPS_256TB         __SHIFTIN(5,TCR_IPS)    /* 48 bits (256 TB) */
-#define  TCR_IPS_16TB          __SHIFTIN(4,TCR_IPS)    /* 44 bits  (16 TB) */
-#define  TCR_IPS_4TB           __SHIFTIN(3,TCR_IPS)    /* 42 bits  ( 4 TB) */
-#define  TCR_IPS_1TB           __SHIFTIN(2,TCR_IPS)    /* 40 bits  ( 1 TB) */
-#define  TCR_IPS_64GB          __SHIFTIN(1,TCR_IPS)    /* 36 bits  (64 GB) */
-#define  TCR_IPS_4GB           __SHIFTIN(0,TCR_IPS)    /* 32 bits   (4 GB) */
-#define TCR_TG1                        __BITS(31,30)           /* TTBR1 Page Granule Size */
-#define  TCR_TG1_16KB          __SHIFTIN(1,TCR_TG1)    /* 16KB page size */
-#define  TCR_TG1_4KB           __SHIFTIN(2,TCR_TG1)    /* 4KB page size */
-#define  TCR_TG1_64KB          __SHIFTIN(3,TCR_TG1)    /* 64KB page size */
-#define TCR_SH1                        __BITS(29,28)
-#define  TCR_SH1_NONE          __SHIFTIN(0,TCR_SH1)
-#define  TCR_SH1_OUTER         __SHIFTIN(2,TCR_SH1)
-#define  TCR_SH1_INNER         __SHIFTIN(3,TCR_SH1)
-#define TCR_ORGN1              __BITS(27,26)           /* TTBR1 Outer cacheability */
-#define  TCR_ORGN1_NC          __SHIFTIN(0,TCR_ORGN1)  /* Non Cacheable */
-#define  TCR_ORGN1_WB_WA       __SHIFTIN(1,TCR_ORGN1)  /* WriteBack WriteAllocate */
-#define  TCR_ORGN1_WT          __SHIFTIN(2,TCR_ORGN1)  /* WriteThrough */
-#define  TCR_ORGN1_WB          __SHIFTIN(3,TCR_ORGN1)  /* WriteBack */
-#define TCR_IRGN1              __BITS(25,24)           /* TTBR1 Inner cacheability */
-#define  TCR_IRGN1_NC          __SHIFTIN(0,TCR_IRGN1)  /* Non Cacheable */
-#define  TCR_IRGN1_WB_WA       __SHIFTIN(1,TCR_IRGN1)  /* WriteBack WriteAllocate */
-#define  TCR_IRGN1_WT          __SHIFTIN(2,TCR_IRGN1)  /* WriteThrough */
-#define  TCR_IRGN1_WB          __SHIFTIN(3,TCR_IRGN1)  /* WriteBack */
-#define TCR_EPD1               __BIT(23)               /* Walk Disable for TTBR1_EL1 */
-#define TCR_A1                 __BIT(22)               /* ASID is in TTBR1_EL1 */
-#define TCR_T1SZ               __BITS(21,16)           /* Size offset for TTBR1_EL1 */
-#define TCR_TG0                        __BITS(15,14)           /* TTBR0 Page Granule Size */
-#define  TCR_TG0_4KB           __SHIFTIN(0,TCR_TG0)    /* 4KB page size */
-#define  TCR_TG0_64KB          __SHIFTIN(1,TCR_TG0)    /* 64KB page size */
-#define  TCR_TG0_16KB          __SHIFTIN(2,TCR_TG0)    /* 16KB page size */
-#define TCR_SH0                        __BITS(13,12)
-#define  TCR_SH0_NONE          __SHIFTIN(0,TCR_SH0)
-#define  TCR_SH0_OUTER         __SHIFTIN(2,TCR_SH0)
-#define  TCR_SH0_INNER         __SHIFTIN(3,TCR_SH0)
-#define TCR_ORGN0              __BITS(11,10)           /* TTBR0 Outer cacheability */
-#define  TCR_ORGN0_NC          __SHIFTIN(0,TCR_ORGN0)  /* Non Cacheable */
-#define  TCR_ORGN0_WB_WA       __SHIFTIN(1,TCR_ORGN0)  /* WriteBack WriteAllocate */
-#define  TCR_ORGN0_WT          __SHIFTIN(2,TCR_ORGN0)  /* WriteThrough */
-#define  TCR_ORGN0_WB          __SHIFTIN(3,TCR_ORGN0)  /* WriteBack */
-#define TCR_IRGN0              __BITS(9,8)             /* TTBR0 Inner cacheability */
-#define  TCR_IRGN0_NC          __SHIFTIN(0,TCR_IRGN0)  /* Non Cacheable */
-#define  TCR_IRGN0_WB_WA       __SHIFTIN(1,TCR_IRGN0)  /* WriteBack WriteAllocate */
-#define  TCR_IRGN0_WT          __SHIFTIN(2,TCR_IRGN0)  /* WriteThrough */
-#define  TCR_IRGN0_WB          __SHIFTIN(3,TCR_IRGN0)  /* WriteBack */
-#define TCR_EPD0               __BIT(7)                /* Walk Disable for TTBR0 */
-#define TCR_T0SZ               __BITS(5,0)             /* Size offset for TTBR0_EL1 */
-
-
-/* TTBR0_EL1, TTBR1_EL1 - Translation Table Base Register */
-#define TTBR_ASID              __BITS(63,48)
-#define TTBR_BADDR             __BITS(47,0)
-
 #define TTBR_SEL_VA            __BIT(63)       /* which TTBR is selected */
 
-
 #elif defined(__arm__)
 
 #include <arm/pte.h>



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