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[src/netbsd-9]: src/sys/dev/pci Pull up following revision(s) (requested by m...



details:   https://anonhg.NetBSD.org/src/rev/e12ba25d78e2
branches:  netbsd-9
changeset: 963283:e12ba25d78e2
user:      martin <martin%NetBSD.org@localhost>
date:      Tue Nov 19 13:07:37 2019 +0000

description:
Pull up following revision(s) (requested by msaitoh in ticket #450):

        sys/dev/pci/if_msk.c: revision 1.94
        sys/dev/pci/if_skreg.h: revision 1.27

 Make Yukon EX, FE+, SUPR stable. The code is mainly taken from FreeBSD.

 At least, this change made my own Yukon EX machine (HP ProBook 4501s) much
stable than before.

diffstat:

 sys/dev/pci/if_msk.c   |  64 ++++++++++++++++++++++++++++++++++++++-----------
 sys/dev/pci/if_skreg.h |  20 +++++++++++++--
 2 files changed, 66 insertions(+), 18 deletions(-)

diffs (180 lines):

diff -r 0c0b8bc71e35 -r e12ba25d78e2 sys/dev/pci/if_msk.c
--- a/sys/dev/pci/if_msk.c      Tue Nov 19 13:04:38 2019 +0000
+++ b/sys/dev/pci/if_msk.c      Tue Nov 19 13:07:37 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_msk.c,v 1.91.2.1 2019/10/24 16:19:23 martin Exp $ */
+/* $NetBSD: if_msk.c,v 1.91.2.2 2019/11/19 13:07:37 martin Exp $ */
 /*     $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $     */
 
 /*
@@ -52,7 +52,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.91.2.1 2019/10/24 16:19:23 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.91.2.2 2019/11/19 13:07:37 martin Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -887,10 +887,27 @@
 mskc_reset(struct sk_softc *sc)
 {
        uint32_t imtimer_ticks, reg1;
+       uint16_t status;
        int reg;
 
        DPRINTFN(2, ("mskc_reset\n"));
 
+       /* Disable ASF */
+       if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) {
+               CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0);
+               status = CSR_READ_2(sc, SK_Y2_ASF_HCU_CCSR);
+               /* Clear AHB bridge & microcontroller reset. */
+               status &= ~(SK_Y2_ASF_HCU_CSSR_ARB_RST |
+                   SK_Y2_ASF_HCU_CSSR_CPU_RST_MODE);
+               /* Clear ASF microcontroller state. */
+               status &= ~SK_Y2_ASF_HCU_CSSR_UC_STATE_MSK;
+               status &= ~SK_Y2_ASF_HCU_CSSR_CPU_CLK_DIVIDE_MSK;
+               CSR_WRITE_2(sc, SK_Y2_ASF_HCU_CCSR, status);
+               CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0);
+       } else
+               CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET);
+       CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF);
+
        CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET);
        CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET);
 
@@ -963,10 +980,6 @@
        DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n",
                     CSR_READ_2(sc, SK_LINK_CTRL)));
 
-       /* Disable ASF */
-       CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET);
-       CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF);
-
        /* Clear I2C IRQ noise */
        CSR_WRITE_4(sc, SK_I2CHWIRQ, 1);
 
@@ -1102,9 +1115,9 @@
 {
        /* GMAC and GPHY Reset */
        SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
-       SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
+       SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
        DELAY(1000);
-       SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR);
+       SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR);
        SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
                      SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
 }
@@ -2410,17 +2423,31 @@
 
        /* Configure RX MAC FIFO */
        SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
-       SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON |
-           SK_RFCTL_FIFO_FLUSH_ON);
-
-       /* Increase flush threshold to 64 bytes */
-       SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
-           SK_RFCTL_FIFO_THRESHOLD + 1);
+       v =  SK_RFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
+       if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_FE_P))
+               v |= SK_RFCTL_RX_OVER_ON;
+       SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
+
+       if ((sc->sk_type == SK_YUKON_FE_P) &&
+           (sc->sk_rev == SK_YUKON_FE_P_REV_A0))
+               v = 0x178; /* Magic value */
+       else {
+               /* Increase flush threshold to 64 bytes */
+               v = SK_RFCTL_FIFO_THRESHOLD + 1;
+       }
+       SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, v);
 
        /* Configure TX MAC FIFO */
        SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
        SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
 
+       if ((sc->sk_type == SK_YUKON_FE_P) &&
+           (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) {
+               v = SK_IF_READ_2(sc_if, 0, SK_TXMF1_END);
+               v &= ~SK_TXEND_WM_ON;
+               SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_END, v);
+       }       
+
 #if 1
        SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN);
 #endif
@@ -2457,7 +2484,7 @@
        /* Configure transmit arbiter(s) */
        SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON);
 #if 0
-           SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON);
+/*         SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); */
 #endif
 
        if (sc->sk_ramsize) {
@@ -2565,6 +2592,13 @@
        SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX,
            sc_if->sk_cdata.sk_rx_prod);
 
+       
+       if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) {
+               /* Disable flushing of non-ASF packets. */
+               SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST,
+                   SK_RFCTL_RX_MACSEC_FLUSH_OFF);
+       }
+
        /* Configure interrupt handling */
        if (sc_if->sk_port == SK_PORT_A)
                sc->sk_intrmask |= SK_Y2_INTRS1;
diff -r 0c0b8bc71e35 -r e12ba25d78e2 sys/dev/pci/if_skreg.h
--- a/sys/dev/pci/if_skreg.h    Tue Nov 19 13:04:38 2019 +0000
+++ b/sys/dev/pci/if_skreg.h    Tue Nov 19 13:07:37 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_skreg.h,v 1.26 2019/03/05 08:25:02 msaitoh Exp $ */
+/* $NetBSD: if_skreg.h,v 1.26.4.1 2019/11/19 13:07:37 martin Exp $ */
 
 /*-
  * Copyright (c) 2003 The NetBSD Foundation, Inc.
@@ -1112,7 +1112,11 @@
 #define SK_RXMF1_READ_LEVEL    0x0C78
 
 /* Receive MAC FIFO 1 Control/Test */
-#define SK_RFCTL_WR_PTR_TST_ON 0x00004000      /* Write pointer test on*/
+#define SK_RFCTL_RX_MACSEC_FLUSH_ON  0x00800000
+#define SK_RFCTL_RX_MACSEC_FLUSH_OFF 0x00400000
+#define SK_RFCTL_RX_OVER_ON    0x00080000      /* Flush on RX Overrun on */
+#define SK_RFCTL_RX_OVER_OFF   0x00040000      /* Flush on RX Overrun off */
+#define SK_RFCTL_WR_PTR_TST_ON 0x00004000      /* Write pointer test on */
 #define SK_RFCTL_WR_PTR_TST_OFF        0x00002000      /* Write pointer test off */
 #define SK_RFCTL_WR_PTR_STEP   0x00001000      /* Write pointer increment */
 #define SK_RFCTL_RD_PTR_TST_ON 0x00000400      /* Read pointer test on */
@@ -1199,6 +1203,9 @@
 #define SK_TXMF1_RESTART_PTR   0x0D74
 #define SK_TXMF1_READ_LEVEL    0x0D78
 
+/* Transmit MAC FIFO End Address */
+#define SK_TXEND_WM_ON         0x00000003      /* ??? */
+
 /* Transmit MAC FIFO Control/Test */
 #define SK_TFCTL_WR_PTR_TST_ON 0x00004000      /* Write pointer test on*/
 #define SK_TFCTL_WR_PTR_TST_OFF        0x00002000      /* Write pointer test off */
@@ -1275,9 +1282,16 @@
 #define SK_TSTAMP_STOP         0x02
 #define SK_TSTAMP_START                0x04
 
+#define SK_Y2_CPU_WDOG         0x0e48
+
 #define SK_Y2_ASF_CSR          0x0e68
+#define SK_Y2_ASF_RESET                0x08
 
-#define SK_Y2_ASF_RESET                0x08
+#define SK_Y2_ASF_HCU_CCSR     0x0e68
+#define SK_Y2_ASF_HCU_CSSR_ARB_RST     __BIT(9)
+#define SK_Y2_ASF_HCU_CSSR_CPU_RST_MODE        __BIT(8)
+#define SK_Y2_ASF_HCU_CSSR_CPU_CLK_DIVIDE_MSK  __BITS(4, 3)
+#define SK_Y2_ASF_HCU_CSSR_UC_STATE_MSK        __BITS(1, 0)
 
 #define SK_Y2_LEV_ITIMERINIT   0x0eb0
 #define SK_Y2_LEV_ITIMERCTL    0x0eb8



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