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[src/netbsd-9]: src/sys/arch Pull up following revision(s) (requested by jmcn...



details:   https://anonhg.NetBSD.org/src/rev/44c4f5811936
branches:  netbsd-9
changeset: 963166:44c4f5811936
user:      martin <martin%NetBSD.org@localhost>
date:      Wed Oct 23 19:14:19 2019 +0000

description:
Pull up following revision(s) (requested by jmcneill in ticket #359):

        sys/arch/aarch64/aarch64/locore.S: revision 1.42
        sys/arch/aarch64/aarch64/locore.S: revision 1.43
        sys/arch/aarch64/aarch64/locore.S: revision 1.44
        sys/arch/arm/fdt/cpu_fdt.c: revision 1.28
        sys/arch/aarch64/include/cpu.h: revision 1.14
        sys/arch/aarch64/include/param.h: revision 1.12
        sys/arch/arm/arm32/cpu.c: revision 1.133
        sys/arch/arm/arm32/cpu.c: revision 1.134
        sys/arch/arm/include/cpu.h: revision 1.101
        sys/arch/arm/acpi/cpu_acpi.c: revision 1.7
        sys/arch/aarch64/aarch64/cpu.c: revision 1.23
        sys/arch/aarch64/aarch64/cpu.c: revision 1.24
        sys/arch/aarch64/aarch64/cpu.c: revision 1.25

Increase aarch64 MAXCPUS to 256.

 -

Invalidate dcache before polling AP hatched status

 -

Avoid overlap between BP and last AP stack. AP stacks are now in order of
increasing address order.

Spotted by and idea from mlelstv.

 -

Use separate cacheline aligned arrays for mbox and hatched as before.

 -

cpu_hatched_p only for MULTIPROCESSOR

diffstat:

 sys/arch/aarch64/aarch64/cpu.c    |  47 ++++++++++++++++++++++++++------------
 sys/arch/aarch64/aarch64/locore.S |  47 +++++++++++++++++++++-----------------
 sys/arch/aarch64/include/cpu.h    |   4 +-
 sys/arch/aarch64/include/param.h  |   4 ++-
 sys/arch/arm/acpi/cpu_acpi.c      |  12 ++++----
 sys/arch/arm/arm32/cpu.c          |  15 +++++++++--
 sys/arch/arm/fdt/cpu_fdt.c        |   7 ++---
 sys/arch/arm/include/cpu.h        |   4 +-
 8 files changed, 86 insertions(+), 54 deletions(-)

diffs (truncated from 388 to 300 lines):

diff -r 0dd2ffc9bd5e -r 44c4f5811936 sys/arch/aarch64/aarch64/cpu.c
--- a/sys/arch/aarch64/aarch64/cpu.c    Wed Oct 23 18:09:18 2019 +0000
+++ b/sys/arch/aarch64/aarch64/cpu.c    Wed Oct 23 19:14:19 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.20 2019/07/16 20:29:53 jmcneill Exp $ */
+/* $NetBSD: cpu.c,v 1.20.2.1 2019/10/23 19:14:19 martin Exp $ */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.20 2019/07/16 20:29:53 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.20.2.1 2019/10/23 19:14:19 martin Exp $");
 
 #include "locators.h"
 #include "opt_arm_debug.h"
@@ -69,8 +69,8 @@
 #ifdef MULTIPROCESSOR
 uint64_t cpu_mpidr[MAXCPUS];
 
-volatile u_int arm_cpu_hatched __cacheline_aligned = 0;
-volatile uint32_t arm_cpu_mbox __cacheline_aligned = 0;
+volatile u_int aarch64_cpu_mbox[howmany(MAXCPUS, sizeof(u_int))] __cacheline_aligned = { 0 };
+volatile u_int aarch64_cpu_hatched[howmany(MAXCPUS, sizeof(u_int))] __cacheline_aligned = { 0 };
 u_int arm_cpu_max = 1;
 
 static kmutex_t cpu_hatch_lock;
@@ -126,7 +126,7 @@
                /* ci_id is stored by own cpus when hatching */
 
                cpu_info[ncpu] = ci;
-               if ((arm_cpu_hatched & __BIT(unit)) == 0) {
+               if (cpu_hatched_p(unit) == 0) {
                        ci->ci_dev = dv;
                        dv->dv_private = ci;
                        ci->ci_index = -1;
@@ -499,27 +499,33 @@
 void
 cpu_boot_secondary_processors(void)
 {
+       u_int n, bit;
+
        if ((boothowto & RB_MD1) != 0)
                return;
 
        mutex_init(&cpu_hatch_lock, MUTEX_DEFAULT, IPL_NONE);
 
-       VPRINTF("%s: writing mbox with %#x\n", __func__, arm_cpu_hatched);
+       VPRINTF("%s: starting secondary processors\n", __func__);
 
        /* send mbox to have secondary processors do cpu_hatch() */
-       atomic_or_32(&arm_cpu_mbox, arm_cpu_hatched);
+       for (n = 0; n < __arraycount(aarch64_cpu_mbox); n++)
+               atomic_or_uint(&aarch64_cpu_mbox[n], aarch64_cpu_hatched[n]);
        __asm __volatile ("sev; sev; sev");
 
        /* wait all cpus have done cpu_hatch() */
-       while (membar_consumer(), arm_cpu_mbox & arm_cpu_hatched) {
-               __asm __volatile ("wfe");
+       for (n = 0; n < __arraycount(aarch64_cpu_mbox); n++) {
+               while (membar_consumer(), aarch64_cpu_mbox[n] & aarch64_cpu_hatched[n]) {
+                       __asm __volatile ("wfe");
+               }
+               /* Add processors to kcpuset */
+               for (bit = 0; bit < 32; bit++) {
+                       if (aarch64_cpu_hatched[n] & __BIT(bit))
+                               kcpuset_set(kcpuset_attached, n * 32 + bit);
+               }
        }
 
        VPRINTF("%s: secondary processors hatched\n", __func__);
-
-       /* add available processors to kcpuset */
-       uint32_t mbox = arm_cpu_hatched;
-       kcpuset_export_u32(kcpuset_attached, &mbox, sizeof(mbox));
 }
 
 void
@@ -549,12 +555,23 @@
 #endif
 
        /*
-        * clear my bit of arm_cpu_mbox to tell cpu_boot_secondary_processors().
+        * clear my bit of aarch64_cpu_mbox to tell cpu_boot_secondary_processors().
         * there are cpu0,1,2,3, and if cpu2 is unresponsive,
         * ci_index are each cpu0=0, cpu1=1, cpu2=undef, cpu3=2.
         * therefore we have to use device_unit instead of ci_index for mbox.
         */
-       atomic_and_32(&arm_cpu_mbox, ~__BIT(device_unit(ci->ci_dev)));
+       const u_int off = device_unit(ci->ci_dev) / 32;
+       const u_int bit = device_unit(ci->ci_dev) % 32;
+       atomic_and_uint(&aarch64_cpu_mbox[off], ~__BIT(bit));
        __asm __volatile ("sev; sev; sev");
 }
+
+bool
+cpu_hatched_p(u_int cpuindex)
+{
+       const u_int off = cpuindex / 32;
+       const u_int bit = cpuindex % 32;
+       membar_consumer();
+       return (aarch64_cpu_hatched[off] & __BIT(bit)) != 0;
+}
 #endif /* MULTIPROCESSOR */
diff -r 0dd2ffc9bd5e -r 44c4f5811936 sys/arch/aarch64/aarch64/locore.S
--- a/sys/arch/aarch64/aarch64/locore.S Wed Oct 23 18:09:18 2019 +0000
+++ b/sys/arch/aarch64/aarch64/locore.S Wed Oct 23 19:14:19 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.S,v 1.39.2.1 2019/09/22 12:39:36 martin Exp $   */
+/*     $NetBSD: locore.S,v 1.39.2.2 2019/10/23 19:14:19 martin Exp $   */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -38,7 +38,7 @@
 #include <aarch64/hypervisor.h>
 #include "assym.h"
 
-RCSID("$NetBSD: locore.S,v 1.39.2.1 2019/09/22 12:39:36 martin Exp $")
+RCSID("$NetBSD: locore.S,v 1.39.2.2 2019/10/23 19:14:19 martin Exp $")
 
 
 /*#define DEBUG_LOCORE                 /* debug print */
@@ -361,28 +361,23 @@
        mov     x1, xzr
 1:
        add     x1, x1, #1
-       cmp     x1, MAXCPUS             /* cpuindex >= MAXCPUS ? */
+       cmp     x1, #MAXCPUS            /* cpuindex >= MAXCPUS ? */
        bge     toomanycpus
        ldr     x2, [x0, x1, lsl #3]    /* cpu_mpidr[cpuindex] */
        cmp     x2, x3                  /* == mpidr_el1 & MPIDR_AFF ? */
        bne     1b
 
        mov     x27, x1                 /* x27 = cpuindex */
-       mov     x0, #1
-       lsl     x28, x0, x27            /* x28 = 1 << cpuindex */
-
 
        /*
         * x27 = cpuindex
-        * x28 = (1 << cpuindex)
         */
 
        /* set stack pointer for boot */
        mov     x1, #BOOT_AP_STACKSIZE
        mul     x1, x1, x27
-       ADDR    x0, bootstk_cpus
-       sub     sp, x0, x1  /* sp = bootstk_cpus-(BOOT_AP_STACKSIZE*cpuindex) */
-
+       ADDR    x0, bootstk
+       add     sp, x0, x1  /* sp = bootstk + (BOOT_AP_STACKSIZE * cpuindex) */
 
        bl      1f
 1:     CPU_DPRINTREG("PC               = ", lr)
@@ -447,28 +442,39 @@
        mrs     x1, mpidr_el1
        str     x1, [x0, #CI_MPIDR]     /* curcpu()->ci_mpidr = mpidr_el1 */
 
-       CPU_DPRINTREG("arm_cpu_hatched |= ", x28)
+       mov     x0, #32
+       udiv    x1, x27, x0
+       ADDR    x0, _C_LABEL(aarch64_cpu_hatched)
+       add     x28, x0, x1, lsl #2     /* x28 = &aarch64_cpu_hatched[cpuindex/32] */
+       mov     x0, #1
+       mov     x2, #32
+       msub    x1, x1, x2, x27
+       lsl     x29, x0, x1             /* x29 = 1 << (cpuindex % 32) */
 
        /*
-        * atomic_or_32(&arm_cpu_hatched, (1 << cpuindex))
+        * atomic_or_uint(&aarch64_cpu_hatched[cpuindex/32], 1<<cpuindex%32)
         * to tell my activity to primary processor.
         */
-       ADDR    x0, _C_LABEL(arm_cpu_hatched)
-       mov     x1, x28
-       bl      _C_LABEL(atomic_or_32)  /* hatched! */
+       mov     x0, x28
+       mov     x1, x29
+       bl      _C_LABEL(atomic_or_uint)        /* hatched! */
+       dsb     sy
        sev
 
-       /* wait for my bit of arm_cpu_mbox become true */
-       ADDR    x0, _C_LABEL(arm_cpu_mbox)
+       mov     x0, #32
+       udiv    x1, x27, x0
+       ADDR    x0, _C_LABEL(aarch64_cpu_mbox)
+       add     x28, x0, x1, lsl #2     /* x28 = &aarch64_cpu_mbox[cpuindex/32] */
+
+       /* wait for the mailbox start bit to become true */
 1:
        dmb     sy
-       ldr     x20, [x0]
-       tst     x20, x28
+       ldr     w20, [x28]
+       tst     w20, w29
        bne     9f
        wfe
        b       1b
 9:
-//     CPU_DPRINTREG("got arm_cpu_mbox = ", x20)
 
        /* fill my cpu_info */
        mrs     x0, tpidr_el1           /* curcpu() */
@@ -1042,7 +1048,6 @@
 
 #ifdef MULTIPROCESSOR
        .space  BOOT_AP_STACKSIZE * (MAXCPUS - 1)
-bootstk_cpus:
 #endif
 
        .section ".init_pagetable", "aw", %nobits
diff -r 0dd2ffc9bd5e -r 44c4f5811936 sys/arch/aarch64/include/cpu.h
--- a/sys/arch/aarch64/include/cpu.h    Wed Oct 23 18:09:18 2019 +0000
+++ b/sys/arch/aarch64/include/cpu.h    Wed Oct 23 19:14:19 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.13 2018/12/21 08:01:01 ryo Exp $ */
+/* $NetBSD: cpu.h,v 1.13.4.1 2019/10/23 19:14:19 martin Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -126,8 +126,8 @@
 void cpu_hatch(struct cpu_info *);
 
 extern struct cpu_info *cpu_info[];
-extern volatile u_int arm_cpu_hatched; /* MULTIPROCESSOR */
 extern uint64_t cpu_mpidr[];           /* MULTIPROCESSOR */
+bool cpu_hatched_p(u_int);             /* MULTIPROCESSOR */
 
 #define CPU_INFO_ITERATOR      cpuid_t
 #ifdef MULTIPROCESSOR
diff -r 0dd2ffc9bd5e -r 44c4f5811936 sys/arch/aarch64/include/param.h
--- a/sys/arch/aarch64/include/param.h  Wed Oct 23 18:09:18 2019 +0000
+++ b/sys/arch/aarch64/include/param.h  Wed Oct 23 19:14:19 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: param.h,v 1.11 2019/01/19 09:11:55 skrll Exp $ */
+/* $NetBSD: param.h,v 1.11.4.1 2019/10/23 19:14:19 martin Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -129,6 +129,8 @@
 #define COHERENCY_UNIT         128
 #define CACHE_LINE_SIZE                128
 
+#define MAXCPUS                        256
+
 #ifdef _KERNEL
 
 #ifndef __HIDE_DELAY
diff -r 0dd2ffc9bd5e -r 44c4f5811936 sys/arch/arm/acpi/cpu_acpi.c
--- a/sys/arch/arm/acpi/cpu_acpi.c      Wed Oct 23 18:09:18 2019 +0000
+++ b/sys/arch/arm/acpi/cpu_acpi.c      Wed Oct 23 19:14:19 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_acpi.c,v 1.6 2019/05/23 15:54:28 ryo Exp $ */
+/* $NetBSD: cpu_acpi.c,v 1.6.4.1 2019/10/23 19:14:19 martin Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
 #include "opt_multiprocessor.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_acpi.c,v 1.6 2019/05/23 15:54:28 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_acpi.c,v 1.6.4.1 2019/10/23 19:14:19 martin Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -41,6 +41,7 @@
 #include <sys/device.h>
 #include <sys/interrupt.h>
 #include <sys/kcpuset.h>
+#include <sys/reboot.h>
 
 #include <dev/acpi/acpireg.h>
 #include <dev/acpi/acpivar.h>
@@ -99,7 +100,7 @@
        struct cpu_info *ci = &cpu_info_store[unit];
 
 #ifdef MULTIPROCESSOR
-       if (cpu_mpidr_aff_read() != mpidr) {
+       if (cpu_mpidr_aff_read() != mpidr && (boothowto & RB_MD1) == 0) {
                const u_int cpuindex = device_unit(self);
                int error;
 
@@ -116,9 +117,8 @@
                __asm __volatile("sev" ::: "memory");
 
                for (u_int i = 0x10000000; i > 0; i--) {
-                       membar_consumer();
-                       if (arm_cpu_hatched & __BIT(cpuindex))
-                               break;
+                       if (cpu_hatched_p(cpuindex))
+                                break;
                }
        }
 #endif /* MULTIPROCESSOR */
diff -r 0dd2ffc9bd5e -r 44c4f5811936 sys/arch/arm/arm32/cpu.c
--- a/sys/arch/arm/arm32/cpu.c  Wed Oct 23 18:09:18 2019 +0000



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