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[src/netbsd-9]: src/sys/dev Pull up following revision(s) (requested by msait...



details:   https://anonhg.NetBSD.org/src/rev/ff7617f36b13
branches:  netbsd-9
changeset: 963722:ff7617f36b13
user:      martin <martin%NetBSD.org@localhost>
date:      Thu Mar 19 19:21:37 2020 +0000

description:
Pull up following revision(s) (requested by msaitoh in ticket #786):

        sys/dev/pci/if_nfe.c: revision 1.77
        sys/dev/pci/if_nfe.c: revision 1.78
        sys/dev/mii/atphy.c: revision 1.28
        sys/dev/mii/atphy.c: revision 1.29
        sys/dev/mii/miidevs: revision 1.166

  Use unsigned to avoid undefined behavior. Found by kUBSan.
0x001374 is non-bitreversed value of Attansic OUI(0x00c82e).
Attansic/Atheros correctly uses ID1 and ID2 register, so delete all 0x001374
related entries.

Improve error check:
- We check PHY register read error correctly (timeout and NFE_PHY_ERROR), so
   don't check NFE_PHY_DATA register's value with 0xffffffff or 0. At least,
   some registers may have 0.
- Check NFE_PHY_ERROR bit in nfe_miibus_writereg().
- Improve debug printf

Fix a bug that atphy(4) doesn't work with Attansic L2 rev. 1.
Reported by Rocky Hotas.

- On ASUS M2N-MX SE Plus (NVIDIA MCP61 with Attansic L2 rev. 1), changing
   debug port 0x29's value makes the next PHY read fail with error.  Read any
   register to ignore this problem if the PHY is Attansic L2 revision 1.
   I don't know if this problem is from L2 rev. 1 itself or from the
   combination because I have only one machine which has L2 rev. "1".
   At least, ASUS eee pc 900 (Attansic L2 rev. "2") has no this problem.
- Add comment. AR8021 document has no description about the power saving
   control register(debug port 0x29).
- Add comment. AR8031 document says the lower 14 bits are reserved and the
   default value is 0x36d0. Shouldn't we clear those bits?
- I have no document neither L1(F1) nor L2(F2), so I don't know whether the
   debug port access is correct or not.
Tested with the following machines:
- ASUS P5B SE,         L1 rev. 5,            age(4)
- ASUS K50IJ,          L1 rev. 9,            ale(4)
- ASUS eee pc 900,     L2 rev. 2,            lii(4)
- ASUS M2N-MX SE Plus, L2 rev. 1,            nfe(4)
- Intel DP55WB,        82578(AR8021 rev. 2), wm(4)
- Dell inspiron 14z,   AR0835 rev. 9,        alc(4)

diffstat:

 sys/dev/mii/atphy.c  |  27 +++++++++++++++++++++++----
 sys/dev/mii/miidevs  |   9 ++-------
 sys/dev/pci/if_nfe.c |  29 +++++++++++++++++------------
 3 files changed, 42 insertions(+), 23 deletions(-)

diffs (173 lines):

diff -r d1fc930129e0 -r ff7617f36b13 sys/dev/mii/atphy.c
--- a/sys/dev/mii/atphy.c       Thu Mar 19 19:18:27 2020 +0000
+++ b/sys/dev/mii/atphy.c       Thu Mar 19 19:21:37 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: atphy.c,v 1.22.4.1 2019/11/21 14:00:49 martin Exp $ */
+/*     $NetBSD: atphy.c,v 1.22.4.2 2020/03/19 19:21:37 martin Exp $ */
 /*     $OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $  */
 
 /*-
@@ -33,7 +33,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.22.4.1 2019/11/21 14:00:49 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.22.4.2 2020/03/19 19:21:37 martin Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -91,7 +91,6 @@
 };
 
 static const struct mii_phydesc atphys[] = {
-       MII_PHY_DESC(ATHEROS, F1),
        MII_PHY_DESC(ATTANSIC, L1),
        MII_PHY_DESC(ATTANSIC, L2),
        MII_PHY_DESC(ATTANSIC, AR8021),
@@ -358,10 +357,30 @@
        uint16_t reg;
        int i;
 
-       /* Take PHY out of power down mode. */
+       /*
+        * Take PHY out of power down mode.
+        *
+        * XXX AR8021 document has no description about the power saving
+        * control register. Shouldn't we write it?
+        */
        PHY_WRITE(sc, 29, 0x29);
+       /*
+        * XXX AR8031 document says the lower 14 bits are reserved and the
+        * default value is 0x36d0. Shouldn't we clear those bits?
+        * I have no document neither L1(F1) nor L2(F2).
+        */
        PHY_WRITE(sc, 30, 0);
 
+       if ((sc->mii_mpd_model == MII_MODEL_ATTANSIC_L2)
+           && (sc->mii_mpd_rev == 1)) {
+               /*
+                * On NVIDIA MCP61 with Attansic L2 rev. 1, changing debug
+                * port 0x29's value makes the next PHY read fail with error.
+                * This is observed on ASUS M2N-MX SE Plus. Read any register
+                * to ignore this problem.
+                */
+               (void)PHY_READ(sc, ATPHY_SCR, &reg);
+       }
        PHY_READ(sc, ATPHY_SCR, &reg);
        /* Enable automatic crossover. */
        reg |= ATPHY_SCR_AUTO_X_MODE;
diff -r d1fc930129e0 -r ff7617f36b13 sys/dev/mii/miidevs
--- a/sys/dev/mii/miidevs       Thu Mar 19 19:18:27 2020 +0000
+++ b/sys/dev/mii/miidevs       Thu Mar 19 19:21:37 2020 +0000
@@ -1,4 +1,4 @@
-$NetBSD: miidevs,v 1.153.2.4 2019/11/25 16:53:29 martin Exp $
+$NetBSD: miidevs,v 1.153.2.5 2020/03/19 19:21:37 martin Exp $
 
 /*-
  * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
@@ -64,7 +64,6 @@
 oui ALTIMA                     0x0010a9        Altima Communications
 oui ENABLESEMI                 0x0010dd        Enable Semiconductor
 oui SUNPLUS                    0x001105        Sunplus Technology
-oui ATHEROS                    0x001374        Atheros
 oui TERANETICS                 0x0014a6        Teranetics
 oui RALINK2                    0x0017a5        Ralink Technology
 oui AQUANTIA                   0x0017b6        Aquantia Corporation
@@ -148,11 +147,7 @@
 model AMLOGIC GXL              0x0000 Meson GXL internal PHY
 model xxAMLOGIC GXL            0x0000 Meson GXL internal PHY
 
-/* Atheros PHYs */
-model ATHEROS F1               0x0001 F1 10/100/1000 PHY
-model ATHEROS F2               0x0002 F2 10/100 PHY
-
-/* Attansic PHYs */
+/* Attansic/Atheros PHYs */
 model ATTANSIC L1              0x0001 L1 10/100/1000 PHY
 model ATTANSIC L2              0x0002 L2 10/100 PHY
 model ATTANSIC AR8021          0x0004 Atheros AR8021 10/100/1000 PHY
diff -r d1fc930129e0 -r ff7617f36b13 sys/dev/pci/if_nfe.c
--- a/sys/dev/pci/if_nfe.c      Thu Mar 19 19:18:27 2020 +0000
+++ b/sys/dev/pci/if_nfe.c      Thu Mar 19 19:21:37 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_nfe.c,v 1.71 2019/07/09 08:46:59 msaitoh Exp $      */
+/*     $NetBSD: if_nfe.c,v 1.71.2.1 2020/03/19 19:21:37 martin Exp $   */
 /*     $OpenBSD: if_nfe.c,v 1.77 2008/02/05 16:52:50 brad Exp $        */
 
 /*-
@@ -21,7 +21,7 @@
 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.71 2019/07/09 08:46:59 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_nfe.c,v 1.71.2.1 2020/03/19 19:21:37 martin Exp $");
 
 #include "opt_inet.h"
 #include "vlan.h"
@@ -546,20 +546,19 @@
                        break;
        }
        if (ntries == 1000) {
-               DPRINTFN(2, ("%s: timeout waiting for PHY\n",
-                   device_xname(sc->sc_dev)));
+               DPRINTFN(2, ("%s: timeout waiting for PHY read (%d, %d)\n",
+                   device_xname(sc->sc_dev), phy, reg));
                return ETIMEDOUT;
        }
 
        if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
-               DPRINTFN(2, ("%s: could not read PHY\n",
-                   device_xname(sc->sc_dev)));
+               DPRINTFN(2, ("%s: could not read PHY (%d, %d)\n",
+                   device_xname(sc->sc_dev), phy, reg));
                return -1;
        }
 
        data = NFE_READ(sc, NFE_PHY_DATA);
-       if (data != 0xffffffff && data != 0)
-               sc->mii_phyaddr = phy;
+       sc->mii_phyaddr = phy;
 
        DPRINTFN(2, ("%s: mii read phy %d reg 0x%x data 0x%x\n",
            device_xname(sc->sc_dev), phy, reg, data));
@@ -594,10 +593,16 @@
        if (ntries == 1000) {
 #ifdef NFE_DEBUG
                if (nfedebug >= 2)
-                       printf("could not write to PHY\n");
+                       printf("timeout waiting for PHY write (%d, %d)\n",
+                           phy, reg);
 #endif
                return ETIMEDOUT;
        }
+       if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
+               DPRINTFN(2, ("%s: could not write PHY (%d, %d)\n",
+                   device_xname(sc->sc_dev), phy, reg));
+               return -1;
+       }
        return 0;
 }
 
@@ -1923,11 +1928,11 @@
        addr[0] |= 0x01;        /* make sure multicast bit is set */
 
        NFE_WRITE(sc, NFE_MULTIADDR_HI,
-           addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
+           (uint32_t)addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
        NFE_WRITE(sc, NFE_MULTIADDR_LO,
            addr[5] <<  8 | addr[4]);
        NFE_WRITE(sc, NFE_MULTIMASK_HI,
-           mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
+           (uint32_t)mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
        NFE_WRITE(sc, NFE_MULTIMASK_LO,
            mask[5] <<  8 | mask[4]);
 
@@ -1970,7 +1975,7 @@
        NFE_WRITE(sc, NFE_MACADDR_LO,
            addr[5] <<  8 | addr[4]);
        NFE_WRITE(sc, NFE_MACADDR_HI,
-           addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
+           (uint32_t)addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
 }
 
 void



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