[src/trunk]: src/sys/arch/arm/cortex Avoid an extra daif read when dispatchin...

[jakllsch <jakllsch%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/c17f06ea50e8
branches:  trunk
changeset: 959358:c17f06ea50e8
user:      jakllsch <jakllsch%NetBSD.org@localhost>
date:      Tue Feb 09 14:24:14 2021 +0000

description:
Avoid an extra daif read when dispatching interrupts by using
ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros.

diffstat:

 sys/arch/arm/cortex/gic.c |  12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diffs (48 lines):

diff -r bb7067a93a3e -r c17f06ea50e8 sys/arch/arm/cortex/gic.c
--- a/sys/arch/arm/cortex/gic.c Tue Feb 09 13:28:47 2021 +0000
+++ b/sys/arch/arm/cortex/gic.c Tue Feb 09 14:24:14 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: gic.c,v 1.43 2020/12/03 07:45:52 skrll Exp $   */
+/*     $NetBSD: gic.c,v 1.44 2021/02/09 14:24:14 jakllsch Exp $        */
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -34,7 +34,7 @@
 #define _INTR_PRIVATE
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.43 2020/12/03 07:45:52 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.44 2021/02/09 14:24:14 jakllsch Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -367,9 +367,9 @@
                        gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl));
                        ci->ci_cpl = ipl;
                }
-               cpsie(I32_bit);
+               ENABLE_INTERRUPT();
                pic_dispatch(is, tf);
-               cpsid(I32_bit);
+               DISABLE_INTERRUPT();
                gicc_write(sc, GICC_EOIR, iar);
 #ifdef DEBUG
                n++;
@@ -529,7 +529,7 @@
        }
        gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ci->ci_cpl));   // set PMR
        gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable interrupt
-       cpsie(I32_bit);                                 // allow IRQ exceptions
+       ENABLE_INTERRUPT();                             // allow IRQ exceptions
 }
 
 void
@@ -656,7 +656,7 @@
        armgic_set_priority(&sc->sc_pic, ci->ci_cpl);   // set PMR
        gicd_write(sc, GICD_CTRL, GICD_CTRL_Enable);    // enable Distributer
        gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable CPU interrupts
-       cpsie(I32_bit);                                 // allow interrupt exceptions
+       ENABLE_INTERRUPT();                             // allow interrupt exceptions
 
        /*
         * For each line that isn't valid, we set the intrsource for it to