Source-Changes-HG archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

[src/trunk]: src/sys/dev/pci Sync with OpenBSD r1.98. Lots of improvements in...



details:   https://anonhg.NetBSD.org/src/rev/bf6516f4469e
branches:  trunk
changeset: 959063:bf6516f4469e
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sat Jan 30 21:26:32 2021 +0000

description:
Sync with OpenBSD r1.98. Lots of improvements including checksum offload,
hardware vlan tagging, and support for multiple receive queues.

diffstat:

 sys/dev/pci/files.pci |     4 +-
 sys/dev/pci/if_mcx.c  |  3688 +++++++++++++++++++++++++++++++++++++-----------
 2 files changed, 2839 insertions(+), 853 deletions(-)

diffs (truncated from 5421 to 300 lines):

diff -r a1b3580b9fe8 -r bf6516f4469e sys/dev/pci/files.pci
--- a/sys/dev/pci/files.pci     Sat Jan 30 21:25:10 2021 +0000
+++ b/sys/dev/pci/files.pci     Sat Jan 30 21:26:32 2021 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: files.pci,v 1.432 2020/10/14 10:19:11 ryo Exp $
+#      $NetBSD: files.pci,v 1.433 2021/01/30 21:26:32 jmcneill Exp $
 #
 # Config file and device description for machine-independent PCI code.
 # Included by ports that need it.  Requires that the SCSI files be
@@ -681,7 +681,7 @@
                        WM_DISABLE_MSIX
 
 # Mellanox 5th generation Ethernet devices
-device mcx: ether, ifnet, arp
+device mcx: ether, ifnet, arp, toeplitz
 attach mcx at pci
 file   dev/pci/if_mcx.c                mcx
 
diff -r a1b3580b9fe8 -r bf6516f4469e sys/dev/pci/if_mcx.c
--- a/sys/dev/pci/if_mcx.c      Sat Jan 30 21:25:10 2021 +0000
+++ b/sys/dev/pci/if_mcx.c      Sat Jan 30 21:26:32 2021 +0000
@@ -1,5 +1,5 @@
-/*     $NetBSD: if_mcx.c,v 1.14 2020/05/25 10:35:17 jmcneill Exp $ */
-/*     $OpenBSD: if_mcx.c,v 1.44 2020/04/24 07:28:37 mestre Exp $ */
+/*     $NetBSD: if_mcx.c,v 1.15 2021/01/30 21:26:32 jmcneill Exp $ */
+/*     $OpenBSD: if_mcx.c,v 1.98 2021/01/27 07:46:11 dlg Exp $ */
 
 /*
  * Copyright (c) 2017 David Gwynne <dlg%openbsd.org@localhost>
@@ -23,7 +23,7 @@
 #endif
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_mcx.c,v 1.14 2020/05/25 10:35:17 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_mcx.c,v 1.15 2021/01/30 21:26:32 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -37,8 +37,10 @@
 #include <sys/callout.h>
 #include <sys/workqueue.h>
 #include <sys/atomic.h>
+#include <sys/timetc.h>
 #include <sys/kmem.h>
 #include <sys/bus.h>
+#include <sys/interrupt.h>
 
 #include <machine/intr.h>
 
@@ -46,6 +48,8 @@
 #include <net/if_dl.h>
 #include <net/if_ether.h>
 #include <net/if_media.h>
+#include <net/if_vlanvar.h>
+#include <net/toeplitz.h>
 
 #include <net/bpf.h>
 
@@ -55,6 +59,9 @@
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcidevs.h>
 
+/* TODO: Port kstat key/value stuff to evcnt/sysmon */
+#define        NKSTAT          0
+
 /* XXX This driver is not yet MP-safe; don't claim to be! */
 /* #ifdef NET_MPSAFE */
 /* #define     MCX_MPSAFE      1 */
@@ -63,67 +70,77 @@
 #define        CALLOUT_FLAGS   0
 /* #endif */
 
-#define        MCX_MAX_NINTR   1
-
 #define BUS_DMASYNC_PRERW      (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)
 #define BUS_DMASYNC_POSTRW     (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)
 
 #define MCX_HCA_BAR    PCI_MAPREG_START /* BAR 0 */
 
-#define MCX_FW_VER               0x0000
-#define  MCX_FW_VER_MAJOR(_v)          ((_v) & 0xffff)
-#define  MCX_FW_VER_MINOR(_v)          ((_v) >> 16)
-#define MCX_CMDIF_FW_SUBVER      0x0004
-#define  MCX_FW_VER_SUBMINOR(_v)       ((_v) & 0xffff)
-#define  MCX_CMDIF(_v)                 ((_v) >> 16)
-
-#define MCX_ISSI                1 /* as per the PRM */
-#define MCX_CMD_IF_SUPPORTED    5
-
-#define MCX_HARDMTU             9500
-
-#define MCX_MAX_CQS             2              /* rq, sq */
+#define MCX_FW_VER                     0x0000
+#define  MCX_FW_VER_MAJOR(_v)                  ((_v) & 0xffff)
+#define  MCX_FW_VER_MINOR(_v)                  ((_v) >> 16)
+#define MCX_CMDIF_FW_SUBVER            0x0004
+#define  MCX_FW_VER_SUBMINOR(_v)               ((_v) & 0xffff)
+#define  MCX_CMDIF(_v)                         ((_v) >> 16)
+
+#define MCX_ISSI                       1 /* as per the PRM */
+#define MCX_CMD_IF_SUPPORTED           5
+
+#define MCX_HARDMTU                    9500
+
+#define MCX_PAGE_SHIFT                 12
+#define MCX_PAGE_SIZE                  (1 << MCX_PAGE_SHIFT)
 
 /* queue sizes */
-#define MCX_LOG_EQ_SIZE                 6              /* one page */
-#define MCX_LOG_CQ_SIZE                 12
-#define MCX_LOG_RQ_SIZE                 10
-#define MCX_LOG_SQ_SIZE                 11
+#define MCX_LOG_EQ_SIZE                        7
+#define MCX_LOG_CQ_SIZE                        12
+#define MCX_LOG_RQ_SIZE                        10
+#define MCX_LOG_SQ_SIZE                        11
+
+#define MCX_MAX_QUEUES                 16
 
 /* completion event moderation - about 10khz, or 90% of the cq */
-#define MCX_CQ_MOD_PERIOD      50
-#define MCX_CQ_MOD_COUNTER     (((1 << (MCX_LOG_CQ_SIZE - 1)) * 9) / 10)
-
-#define MCX_LOG_SQ_ENTRY_SIZE   6
-#define MCX_SQ_ENTRY_MAX_SLOTS  4
-#define MCX_SQ_SEGS_PER_SLOT    \
+#define MCX_CQ_MOD_PERIOD              50
+#define MCX_CQ_MOD_COUNTER             \
+       (((1 << (MCX_LOG_CQ_SIZE - 1)) * 9) / 10)
+
+#define MCX_LOG_SQ_ENTRY_SIZE          6
+#define MCX_SQ_ENTRY_MAX_SLOTS         4
+#define MCX_SQ_SEGS_PER_SLOT           \
        (sizeof(struct mcx_sq_entry) / sizeof(struct mcx_sq_entry_seg))
-#define MCX_SQ_MAX_SEGMENTS     \
+#define MCX_SQ_MAX_SEGMENTS            \
        1 + ((MCX_SQ_ENTRY_MAX_SLOTS-1) * MCX_SQ_SEGS_PER_SLOT)
 
-#define MCX_LOG_FLOW_TABLE_SIZE         5
-#define MCX_NUM_STATIC_FLOWS    4      /* promisc, allmulti, ucast, bcast */
-#define MCX_NUM_MCAST_FLOWS    \
+#define MCX_LOG_FLOW_TABLE_SIZE                5
+#define MCX_NUM_STATIC_FLOWS           4 /* promisc, allmulti, ucast, bcast */
+#define MCX_NUM_MCAST_FLOWS            \
        ((1 << MCX_LOG_FLOW_TABLE_SIZE) - MCX_NUM_STATIC_FLOWS)
 
-#define MCX_SQ_INLINE_SIZE      18
+#define MCX_SQ_INLINE_SIZE             18
+CTASSERT(ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN == MCX_SQ_INLINE_SIZE);
 
 /* doorbell offsets */
-#define MCX_CQ_DOORBELL_OFFSET  0
-#define MCX_CQ_DOORBELL_SIZE    16
-#define MCX_RQ_DOORBELL_OFFSET  64
-#define MCX_SQ_DOORBELL_OFFSET  64
-
-#define MCX_WQ_DOORBELL_MASK    0xffff
+#define MCX_DOORBELL_AREA_SIZE         MCX_PAGE_SIZE
+
+#define MCX_CQ_DOORBELL_BASE           0
+#define MCX_CQ_DOORBELL_STRIDE         64
+
+#define MCX_WQ_DOORBELL_BASE           MCX_PAGE_SIZE/2
+#define MCX_WQ_DOORBELL_STRIDE         64
+/* make sure the doorbells fit */
+CTASSERT(MCX_MAX_QUEUES * MCX_CQ_DOORBELL_STRIDE < MCX_WQ_DOORBELL_BASE);
+CTASSERT(MCX_MAX_QUEUES * MCX_WQ_DOORBELL_STRIDE <
+    MCX_DOORBELL_AREA_SIZE - MCX_WQ_DOORBELL_BASE);
+
+#define MCX_WQ_DOORBELL_MASK           0xffff
 
 /* uar registers */
-#define MCX_UAR_CQ_DOORBELL     0x20
-#define MCX_UAR_EQ_DOORBELL_ARM         0x40
-#define MCX_UAR_EQ_DOORBELL     0x48
-#define MCX_UAR_BF              0x800
-
-#define MCX_CMDQ_ADDR_HI                0x0010
-#define MCX_CMDQ_ADDR_LO                0x0014
+#define MCX_UAR_CQ_DOORBELL            0x20
+#define MCX_UAR_EQ_DOORBELL_ARM                0x40
+#define MCX_UAR_EQ_DOORBELL            0x48
+#define MCX_UAR_BF                     0x800
+
+#define MCX_CMDQ_ADDR_HI               0x0010
+#define MCX_CMDQ_ADDR_LO               0x0014
 #define MCX_CMDQ_ADDR_NMASK            0xfff
 #define MCX_CMDQ_LOG_SIZE(_v)          ((_v) >> 4 & 0xf)
 #define MCX_CMDQ_LOG_STRIDE(_v)                ((_v) >> 0 & 0xf)
@@ -133,138 +150,126 @@
 
 #define MCX_CMDQ_DOORBELL              0x0018
 
-#define MCX_STATE              0x01fc
-#define MCX_STATE_MASK                 (1U << 31)
-#define MCX_STATE_INITIALIZING         (1 << 31)
-#define MCX_STATE_READY                        (0 << 31)
-#define MCX_STATE_INTERFACE_MASK       (0x3 << 24)
-#define MCX_STATE_INTERFACE_FULL_DRIVER        (0x0 << 24)
-#define MCX_STATE_INTERFACE_DISABLED   (0x1 << 24)
-
-#define MCX_INTERNAL_TIMER     0x1000
-#define MCX_INTERNAL_TIMER_H   0x1000
-#define MCX_INTERNAL_TIMER_L   0x1004
-
-#define MCX_CLEAR_INT          0x100c
-
-#define MCX_REG_OP_WRITE       0
-#define MCX_REG_OP_READ                1
-
-#define MCX_REG_PMLP           0x5002
-#define MCX_REG_PMTU           0x5003
-#define MCX_REG_PTYS           0x5004
-#define MCX_REG_PAOS           0x5006
-#define MCX_REG_PFCC           0x5007
-#define MCX_REG_PPCNT          0x5008
-#define MCX_REG_MCIA           0x9014
-
-#define MCX_ETHER_CAP_SGMII    0
-#define MCX_ETHER_CAP_1000_KX  1
-#define MCX_ETHER_CAP_10G_CX4  2
-#define MCX_ETHER_CAP_10G_KX4  3
-#define MCX_ETHER_CAP_10G_KR   4
-#define MCX_ETHER_CAP_20G_KR2  5
-#define MCX_ETHER_CAP_40G_CR4  6
-#define MCX_ETHER_CAP_40G_KR4  7
-#define MCX_ETHER_CAP_56G_R4   8
-#define MCX_ETHER_CAP_10G_CR   12
-#define MCX_ETHER_CAP_10G_SR   13
-#define MCX_ETHER_CAP_10G_LR   14
-#define MCX_ETHER_CAP_40G_SR4  15
-#define MCX_ETHER_CAP_40G_LR4  16
-#define MCX_ETHER_CAP_50G_SR2  18
-#define MCX_ETHER_CAP_100G_CR4 20
-#define MCX_ETHER_CAP_100G_SR4 21
-#define MCX_ETHER_CAP_100G_KR4 22
-#define MCX_ETHER_CAP_100G_LR4 23
-#define MCX_ETHER_CAP_100_TX   24
-#define MCX_ETHER_CAP_1000_T   25
-#define MCX_ETHER_CAP_10G_T    26
-#define MCX_ETHER_CAP_25G_CR   27
-#define MCX_ETHER_CAP_25G_KR   28
-#define MCX_ETHER_CAP_25G_SR   29
-#define MCX_ETHER_CAP_50G_CR2  30
-#define MCX_ETHER_CAP_50G_KR2  31
-
-#define MCX_PAGE_SHIFT         12
-#define MCX_PAGE_SIZE          (1 << MCX_PAGE_SHIFT)
-#define MCX_MAX_CQE            32
-
-#define MCX_CMD_QUERY_HCA_CAP  0x100
-#define MCX_CMD_QUERY_ADAPTER  0x101
-#define MCX_CMD_INIT_HCA       0x102
-#define MCX_CMD_TEARDOWN_HCA   0x103
-#define MCX_CMD_ENABLE_HCA     0x104
-#define MCX_CMD_DISABLE_HCA    0x105
-#define MCX_CMD_QUERY_PAGES    0x107
-#define MCX_CMD_MANAGE_PAGES   0x108
-#define MCX_CMD_SET_HCA_CAP    0x109
-#define MCX_CMD_QUERY_ISSI     0x10a
-#define MCX_CMD_SET_ISSI       0x10b
-#define MCX_CMD_SET_DRIVER_VERSION \
-                               0x10d
-#define MCX_CMD_QUERY_SPECIAL_CONTEXTS \
-                               0x203
-#define MCX_CMD_CREATE_EQ      0x301
-#define MCX_CMD_DESTROY_EQ     0x302
-#define MCX_CMD_CREATE_CQ      0x400
-#define MCX_CMD_DESTROY_CQ     0x401
-#define MCX_CMD_QUERY_NIC_VPORT_CONTEXT \
-                               0x754
+#define MCX_STATE                      0x01fc
+#define MCX_STATE_MASK                         (1U << 31)
+#define MCX_STATE_INITIALIZING                 (1 << 31)
+#define MCX_STATE_READY                                (0 << 31)
+#define MCX_STATE_INTERFACE_MASK               (0x3 << 24)
+#define MCX_STATE_INTERFACE_FULL_DRIVER                (0x0 << 24)
+#define MCX_STATE_INTERFACE_DISABLED           (0x1 << 24)
+
+#define MCX_INTERNAL_TIMER             0x1000
+#define MCX_INTERNAL_TIMER_H           0x1000
+#define MCX_INTERNAL_TIMER_L           0x1004
+
+#define MCX_CLEAR_INT                  0x100c
+
+#define MCX_REG_OP_WRITE               0
+#define MCX_REG_OP_READ                        1
+
+#define MCX_REG_PMLP                   0x5002
+#define MCX_REG_PMTU                   0x5003
+#define MCX_REG_PTYS                   0x5004
+#define MCX_REG_PAOS                   0x5006
+#define MCX_REG_PFCC                   0x5007
+#define MCX_REG_PPCNT                  0x5008
+#define MCX_REG_MTCAP                  0x9009 /* mgmt temp capabilities */
+#define MCX_REG_MTMP                   0x900a /* mgmt temp */
+#define MCX_REG_MCIA                   0x9014
+#define MCX_REG_MCAM                   0x907f
+
+#define MCX_ETHER_CAP_SGMII            0



Home | Main Index | Thread Index | Old Index