[src/trunk]: src/sys/arch/arm/amlogic adapts to some register differences to ...

[ryo <ryo%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/bd4db0d7a777
branches:  trunk
changeset: 958322:bd4db0d7a777
user:      ryo <ryo%NetBSD.org@localhost>
date:      Fri Jan 01 07:17:36 2021 +0000

description:
adapts to some register differences to add support "amlogic,meson-axg-mmc"

diffstat:

 sys/arch/arm/amlogic/mesongx_mmc.c |  32 ++++++++++++++++++++++----------
 1 files changed, 22 insertions(+), 10 deletions(-)

diffs (95 lines):

diff -r b5961044d5c8 -r bd4db0d7a777 sys/arch/arm/amlogic/mesongx_mmc.c
--- a/sys/arch/arm/amlogic/mesongx_mmc.c        Fri Jan 01 07:15:18 2021 +0000
+++ b/sys/arch/arm/amlogic/mesongx_mmc.c        Fri Jan 01 07:17:36 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mesongx_mmc.c,v 1.5 2019/04/21 13:08:48 jmcneill Exp $ */
+/* $NetBSD: mesongx_mmc.c,v 1.6 2021/01/01 07:17:36 ryo Exp $ */
 
 /*-
  * Copyright (c) 2019 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mesongx_mmc.c,v 1.5 2019/04/21 13:08:48 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mesongx_mmc.c,v 1.6 2021/01/01 07:17:36 ryo Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -45,10 +45,14 @@
 #include <dev/fdt/fdtvar.h>
 
 #define        SD_EMMC_CLOCK                   0x00
-#define         CLOCK_CFG_IRQ_SDIO_SLEEP               __BIT(25)
-#define         CLOCK_CFG_ALWAYS_ON                    __BIT(24)
-#define         CLOCK_CFG_RX_DELAY                     __BITS(23,20)
-#define         CLOCK_CFG_TX_DELAY                     __BITS(19,16)
+#define         CLOCK_CFG_V2_IRQ_SDIO_SLEEP            __BIT(25)
+#define         CLOCK_CFG_V2_ALWAYS_ON                 __BIT(24)
+#define         CLOCK_CFG_V2_RX_DELAY                  __BITS(23,20)
+#define         CLOCK_CFG_V2_TX_DELAY                  __BITS(19,16)
+#define         CLOCK_CFG_V3_IRQ_SDIO_SLEEP            __BIT(29)
+#define         CLOCK_CFG_V3_ALWAYS_ON                 __BIT(28)
+#define         CLOCK_CFG_V3_RX_DELAY                  __BITS(27,22)
+#define         CLOCK_CFG_V3_TX_DELAY                  __BITS(21,16)
 #define         CLOCK_CFG_SRAM_PD                      __BITS(15,14)
 #define         CLOCK_CFG_RX_PHASE                     __BITS(13,12)
 #define         CLOCK_CFG_TX_PHASE                     __BITS(11,10)
@@ -56,7 +60,7 @@
 #define         CLOCK_CFG_SRC                          __BITS(7,6)
 #define         CLOCK_CFG_DIV                          __BITS(5,0)
 #define        SD_EMMC_DELAY                   0x04
-#define        SD_EMMC_ADJUST                  0x08
+#define        SD_EMMC_ADJUST                  0x08    /* V2 */
 #define         ADJUST_ADJ_DELAY                       __BITS(21,16)
 #define         ADJUST_CALI_RISE                       __BIT(14)
 #define         ADJUST_ADJ_ENABLE                      __BIT(13)
@@ -66,6 +70,7 @@
 #define         CALOUT_CALI_SETUP                      __BITS(15,8)
 #define         CALOUT_CALI_VLD                        __BIT(7)
 #define         CALOUT_CALI_IDX                        __BITS(5,0)
+#define SD_EMMC_V3_ADJUST              0x0c
 #define        SD_EMMC_START                   0x40
 #define         START_DESC_ADDR                        __BITS(31,2)
 #define         START_DESC_BUSY                        __BIT(1)
@@ -214,6 +219,7 @@
 
        device_t                sc_sdmmc_dev;
        uint32_t                sc_host_ocr;
+       int                     sc_hwtype;
 
        struct sdmmc_command    *sc_cmd;
 
@@ -257,8 +263,9 @@
        bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
 
 static const struct of_compat_data compat_data[] = {
-       { "amlogic,meson-gx-mmc",       1 },
-       { "amlogic,meson-gxbb-mmc",     1 },
+       { "amlogic,meson-gx-mmc",       2 },
+       { "amlogic,meson-gxbb-mmc",     2 },
+       { "amlogic,meson-axg-mmc",      3 },
        { NULL }
 };
 
@@ -280,6 +287,8 @@
        bus_addr_t addr;
        bus_size_t size;
 
+       sc->sc_hwtype = (int)of_search_compatible(phandle, compat_data)->data;
+
        if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
                aprint_error(": couldn't get registers\n");
                return;
@@ -483,7 +492,10 @@
                return ERANGE;
 
        val = MMC_READ(sc, SD_EMMC_CLOCK);
-       val |= CLOCK_CFG_ALWAYS_ON;
+       if (sc->sc_hwtype == 3)
+               val |= CLOCK_CFG_V3_ALWAYS_ON;
+       else
+               val |= CLOCK_CFG_V2_ALWAYS_ON;
        val &= ~CLOCK_CFG_RX_PHASE;
        val |= __SHIFTIN(0, CLOCK_CFG_RX_PHASE);
        val &= ~CLOCK_CFG_TX_PHASE;