Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src-draft/trunk]: src/sys/dev/usb Use delay after a bb_write. This is anoth...
details: https://anonhg.NetBSD.org/src-all/rev/0f9c6f9dd56b
branches: trunk
changeset: 950990:0f9c6f9dd56b
user: Nathanial Sloss <nat%netbsd.org@localhost>
date: Mon Jun 08 05:48:10 2020 +1000
description:
Use delay after a bb_write. This is another attempt at fixing usb
issues with utrwn.
diffstat:
sys/dev/usb/if_urtwn.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 65 insertions(+), 0 deletions(-)
diffs (truncated from 388 to 300 lines):
diff -r 4490e806bbc5 -r 0f9c6f9dd56b sys/dev/usb/if_urtwn.c
--- a/sys/dev/usb/if_urtwn.c Fri Jun 05 04:30:14 2020 +1000
+++ b/sys/dev/usb/if_urtwn.c Mon Jun 08 05:48:10 2020 +1000
@@ -1070,6 +1070,7 @@
DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=%#x, len=%d\n",
device_xname(sc->sc_dev), __func__, error, addr, len));
}
+ DELAY(1);
return error;
}
@@ -1140,6 +1141,7 @@
DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=%#x, len=%d\n",
device_xname(sc->sc_dev), __func__, error, addr, len));
}
+ DELAY(1);
return error;
}
@@ -1259,6 +1261,7 @@
urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
+ DELAY(1000);
}
static void
@@ -1268,6 +1271,7 @@
urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
+ DELAY(1000);
}
static void
@@ -1277,6 +1281,7 @@
urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
+ DELAY(1000);
}
static uint32_t
@@ -2454,6 +2459,7 @@
urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
}
+ DELAY(1000);
/* Set media status to 'No Link'. */
urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK);
@@ -2471,6 +2477,7 @@
R92C_BCN_CTRL_DIS_TSF_UDT0);
}
+ DELAY(1000);
/* Make link LED blink during scan. */
urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink);
@@ -2496,11 +2503,13 @@
reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
+ DELAY(1000);
if (!ISSET(sc->chip, URTWN_CHIP_88E)) {
reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
}
+ DELAY(1000);
/* Set media status to 'No Link'. */
urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK);
@@ -2558,6 +2567,7 @@
break;
}
+ DELAY(1000);
/* Set media status to 'Associated'. */
urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc));
@@ -4653,38 +4663,48 @@
reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);
reg = (reg & ~0x00000003) | 0x2;
urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
+ DELAY(1000);
reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);
reg = (reg & ~0x00300033) | 0x00200022;
urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
+ DELAY(1000);
reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);
reg = (reg & ~0xff000000) | (0x45 << 24);
urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
+ DELAY(1000);
reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
reg = (reg & ~0x000000ff) | 0x23;
urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
+ DELAY(1000);
reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
reg = (reg & ~0x00000030) | (1 << 4);
urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
+ DELAY(1000);
reg = urtwn_bb_read(sc, 0xe74);
reg = (reg & ~0x0c000000) | (2 << 26);
urtwn_bb_write(sc, 0xe74, reg);
+ DELAY(1000);
reg = urtwn_bb_read(sc, 0xe78);
reg = (reg & ~0x0c000000) | (2 << 26);
urtwn_bb_write(sc, 0xe78, reg);
+ DELAY(1000);
reg = urtwn_bb_read(sc, 0xe7c);
reg = (reg & ~0x0c000000) | (2 << 26);
urtwn_bb_write(sc, 0xe7c, reg);
+ DELAY(1000);
reg = urtwn_bb_read(sc, 0xe80);
reg = (reg & ~0x0c000000) | (2 << 26);
urtwn_bb_write(sc, 0xe80, reg);
+ DELAY(1000);
reg = urtwn_bb_read(sc, 0xe88);
reg = (reg & ~0x0c000000) | (2 << 26);
urtwn_bb_write(sc, 0xe88, reg);
+ DELAY(1000);
}
/* Write AGC values. */
@@ -4710,6 +4730,7 @@
urtwn_bb_write(sc, R92C_AFE_CTRL3,
RW(reg, R92C_AFE_XTAL_CTRL_ADDR,
crystalcap | crystalcap << 6));
+ DELAY(1000);
urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb);
} else if (ISSET(sc->chip, URTWN_CHIP_88E)) {
crystalcap = sc->r88e_rom[0xb9];
@@ -4720,12 +4741,14 @@
urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL,
RW(reg, R92C_AFE_XTAL_CTRL_ADDR,
crystalcap | crystalcap << 6));
+ DELAY(1000);
} else {
if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
R92C_HSSI_PARAM2_CCK_HIPWR) {
SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR);
}
}
+ DELAY(1000);
}
static void __noinline
@@ -4800,6 +4823,7 @@
/* Restore RF_ENV control type. */
reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask;
urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved);
+ DELAY(1000);
}
if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
@@ -4952,22 +4976,26 @@
reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]);
urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
+ DELAY(1000);
reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]);
reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);
reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);
urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
+ DELAY(1000);
} else {
reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]);
reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]);
reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);
urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
+ DELAY(1000);
reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);
urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
+ DELAY(1000);
}
/* Write per-OFDM rate Tx power. */
urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
@@ -4975,32 +5003,38 @@
SM(R92C_TXAGC_RATE09, power[ 5]) |
SM(R92C_TXAGC_RATE12, power[ 6]) |
SM(R92C_TXAGC_RATE18, power[ 7]));
+ DELAY(1000);
urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
SM(R92C_TXAGC_RATE24, power[ 8]) |
SM(R92C_TXAGC_RATE36, power[ 9]) |
SM(R92C_TXAGC_RATE48, power[10]) |
SM(R92C_TXAGC_RATE54, power[11]));
+ DELAY(1000);
/* Write per-MCS Tx power. */
urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
SM(R92C_TXAGC_MCS00, power[12]) |
SM(R92C_TXAGC_MCS01, power[13]) |
SM(R92C_TXAGC_MCS02, power[14]) |
SM(R92C_TXAGC_MCS03, power[15]));
+ DELAY(1000);
urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
SM(R92C_TXAGC_MCS04, power[16]) |
SM(R92C_TXAGC_MCS05, power[17]) |
SM(R92C_TXAGC_MCS06, power[18]) |
SM(R92C_TXAGC_MCS07, power[19]));
+ DELAY(1000);
urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
SM(R92C_TXAGC_MCS08, power[20]) |
SM(R92C_TXAGC_MCS09, power[21]) |
SM(R92C_TXAGC_MCS10, power[22]) |
SM(R92C_TXAGC_MCS11, power[23]));
+ DELAY(1000);
urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
SM(R92C_TXAGC_MCS12, power[24]) |
SM(R92C_TXAGC_MCS13, power[25]) |
SM(R92C_TXAGC_MCS14, power[26]) |
SM(R92C_TXAGC_MCS15, power[27]));
+ DELAY(1000);
}
static void
@@ -5249,25 +5283,31 @@
urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ);
+ DELAY(1000);
urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ);
+ DELAY(1000);
/* Set CCK side band. */
reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM);
reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4;
urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);
+ DELAY(1000);
reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF);
reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10;
urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);
+ DELAY(1000);
urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) &
~R92C_FPGA0_ANAPARAM2_CBW20);
+ DELAY(1000);
reg = urtwn_bb_read(sc, 0x818);
reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26;
urtwn_bb_write(sc, 0x818, reg);
+ DELAY(1000);
/* Select 40MHz bandwidth. */
urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
@@ -5278,8 +5318,10 @@
urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ);
+ DELAY(1000);
urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);
+ DELAY(1000);
if (!ISSET(sc->chip, URTWN_CHIP_88E) &&
!ISSET(sc->chip, URTWN_CHIP_92EU)) {
@@ -5287,6 +5329,7 @@
urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |
R92C_FPGA0_ANAPARAM2_CBW20);
}
+ DELAY(1000);
/* Select 20MHz bandwidth. */
urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
@@ -5295,6 +5338,7 @@
ISSET(sc->chip, URTWN_CHIP_92EU) ?
R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20));
}
+ DELAY(1000);
}
static void __noinline
@@ -5354,9 +5398,11 @@
urtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))|
R92C_HSSI_PARAM1_PI);
+ DELAY(1000);
urtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))|
R92C_HSSI_PARAM1_PI);
+ DELAY(1000);
}
attempt = 1;
@@ -5367,6 +5413,7 @@
for (i = 0; i < __arraycount(addaReg); i++) {
Home |
Main Index |
Thread Index |
Old Index