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[src/trunk]: src/sys/dev/pci/ixgbe Check EICR's queue bit instead of IFF_RUNN...



details:   https://anonhg.NetBSD.org/src/rev/d4acaf7730e9
branches:  trunk
changeset: 948310:d4acaf7730e9
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Sat Dec 26 06:02:42 2020 +0000

description:
Check EICR's queue bit instead of IFF_RUNNING. This change fixes a bug that
it might incorrectly enable interrupt when IFF_RUNNING is not set. It also
changes that the TX/RX is not processed if a queue interrupt isn't occurred.

diffstat:

 sys/dev/pci/ixgbe/ixgbe.c |  9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diffs (36 lines):

diff -r fed02414ed80 -r d4acaf7730e9 sys/dev/pci/ixgbe/ixgbe.c
--- a/sys/dev/pci/ixgbe/ixgbe.c Sat Dec 26 06:01:22 2020 +0000
+++ b/sys/dev/pci/ixgbe/ixgbe.c Sat Dec 26 06:02:42 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ixgbe.c,v 1.271 2020/12/26 06:01:22 msaitoh Exp $ */
+/* $NetBSD: ixgbe.c,v 1.272 2020/12/26 06:02:42 msaitoh Exp $ */
 
 /******************************************************************************
 
@@ -5154,7 +5154,6 @@
        struct ix_queue *que = arg;
        struct adapter  *adapter = que->adapter;
        struct ixgbe_hw *hw = &adapter->hw;
-       struct ifnet    *ifp = adapter->ifp;
        struct          tx_ring *txr = adapter->tx_rings;
        bool            reenable_intr = true;
        u32             eicr, eicr_mask;
@@ -5172,14 +5171,16 @@
        eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
 
        adapter->stats.pf.legint.ev_count++;
-       ++que->irqs.ev_count;
        if (eicr == 0) {
                adapter->stats.pf.intzero.ev_count++;
                IXGBE_WRITE_REG(hw, IXGBE_EIMS, eims_orig);
                return 0;
        }
 
-       if ((ifp->if_flags & IFF_RUNNING) != 0) {
+       /* Queue (0) intr */
+       if ((eicr & IXGBE_EIMC_RTX_QUEUE) != 0) {
+               ++que->irqs.ev_count;
+
                /*
                 * The same as ixgbe_msix_que() about
                 * "que->txrx_use_workqueue".



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