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[src/trunk]: src/sys/arch/aarch64/aarch64 For rev 1.14 and before, netbsd32_p...
details: https://anonhg.NetBSD.org/src/rev/fe0bb684ae80
branches: trunk
changeset: 940731:fe0bb684ae80
user: rin <rin%NetBSD.org@localhost>
date: Thu Oct 15 22:41:02 2020 +0000
description:
For rev 1.14 and before, netbsd32_process_write_regs() returns EINVAL
if non-modifiable bits are set in CPSR.
Instead, mask out non-modifiable bits and make this function success
regardless of value in CPSR. New behavior matches that of arm:
https://nxr.netbsd.org/xref/src/sys/arch/arm/arm/process_machdep.c#187
This fixes lib/libc/sys/t_ptrace_wait*:access_regs6 tests, in which
register contents retrieved by PT_GETREGS are set back by PT_SETREGS.
No new regression is observed in full ATF run.
OK ryo
diffstat:
sys/arch/aarch64/aarch64/netbsd32_machdep.c | 9 ++++-----
1 files changed, 4 insertions(+), 5 deletions(-)
diffs (37 lines):
diff -r 7946252abc21 -r fe0bb684ae80 sys/arch/aarch64/aarch64/netbsd32_machdep.c
--- a/sys/arch/aarch64/aarch64/netbsd32_machdep.c Thu Oct 15 22:30:34 2020 +0000
+++ b/sys/arch/aarch64/aarch64/netbsd32_machdep.c Thu Oct 15 22:41:02 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: netbsd32_machdep.c,v 1.14 2020/07/02 13:04:46 rin Exp $ */
+/* $NetBSD: netbsd32_machdep.c,v 1.15 2020/10/15 22:41:02 rin Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.14 2020/07/02 13:04:46 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.15 2020/10/15 22:41:02 rin Exp $");
#if defined(_KERNEL_OPT)
#include "opt_compat_netbsd.h"
@@ -198,8 +198,7 @@
if ((p->p_flag & PK_32) == 0)
return EINVAL;
- if ((regs->r_cpsr & ~(SPSR_NZCV | SPSR_A32_T)) != 0 ||
- regs->r_pc >= VM_MAXUSER_ADDRESS32 ||
+ if (regs->r_pc >= VM_MAXUSER_ADDRESS32 ||
regs->r_sp >= VM_MAXUSER_ADDRESS32)
return EINVAL;
@@ -209,7 +208,7 @@
tf->tf_reg[14] = regs->r_lr; /* r14 = lr */
tf->tf_pc = regs->r_pc; /* r15 = pc */
tf->tf_spsr &= ~(SPSR_NZCV | SPSR_A32_T);
- tf->tf_spsr |= regs->r_cpsr;
+ tf->tf_spsr |= regs->r_cpsr & (SPSR_NZCV | SPSR_A32_T);
/* THUMB CODE? */
if (regs->r_pc & 1)
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