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[src/trunk]: src/sys/arch/aarch64/aarch64 aarch64: switch CPU to the kernel's...
details: https://anonhg.NetBSD.org/src/rev/5a3425bb701e
branches: trunk
changeset: 938284:5a3425bb701e
user: jakllsch <jakllsch%NetBSD.org@localhost>
date: Sat Sep 05 17:49:26 2020 +0000
description:
aarch64: switch CPU to the kernel's byte order during boot
diffstat:
sys/arch/aarch64/aarch64/locore_el2.S | 7 +++++--
sys/arch/aarch64/aarch64/start.S | 31 +++++++++++++++++++++++++++++--
2 files changed, 34 insertions(+), 4 deletions(-)
diffs (81 lines):
diff -r 65a785e3d59c -r 5a3425bb701e sys/arch/aarch64/aarch64/locore_el2.S
--- a/sys/arch/aarch64/aarch64/locore_el2.S Sat Sep 05 17:33:11 2020 +0000
+++ b/sys/arch/aarch64/aarch64/locore_el2.S Sat Sep 05 17:49:26 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_el2.S,v 1.4 2020/08/29 07:17:23 maxv Exp $ */
+/* $NetBSD: locore_el2.S,v 1.5 2020/09/05 17:49:26 jakllsch Exp $ */
/*-
* Copyright (c) 2012-2014 Andrew Turner
@@ -32,7 +32,7 @@
#include <aarch64/hypervisor.h>
#include "assym.h"
-RCSID("$NetBSD: locore_el2.S,v 1.4 2020/08/29 07:17:23 maxv Exp $")
+RCSID("$NetBSD: locore_el2.S,v 1.5 2020/09/05 17:49:26 jakllsch Exp $")
/*
* For use in #include "locore_el2.S".
@@ -75,6 +75,9 @@
/* Set the bits that need to be 1 in SCTLR_EL1. */
ldr x2, .Lsctlr_res1
+#ifdef __AARCH64EB__
+ orr x2, x2, #SCTLR_EE
+#endif
msr sctlr_el1, x2
/* Don't trap to EL2 on FP instructions. */
diff -r 65a785e3d59c -r 5a3425bb701e sys/arch/aarch64/aarch64/start.S
--- a/sys/arch/aarch64/aarch64/start.S Sat Sep 05 17:33:11 2020 +0000
+++ b/sys/arch/aarch64/aarch64/start.S Sat Sep 05 17:49:26 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: start.S,v 1.8 2020/07/16 11:36:35 skrll Exp $ */
+/* $NetBSD: start.S,v 1.9 2020/09/05 17:49:26 jakllsch Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -31,8 +31,9 @@
#include <sys/cdefs.h>
#include <aarch64/asm.h>
+#include "assym.h"
-RCSID("$NetBSD: start.S,v 1.8 2020/07/16 11:36:35 skrll Exp $")
+RCSID("$NetBSD: start.S,v 1.9 2020/09/05 17:49:26 jakllsch Exp $")
/*
* Padding at start of kernel image to make room for 64-byte header
@@ -45,6 +46,32 @@
*/
.global start
start:
+ mrs x8, CurrentEL
+ lsr x8, x8, #2
+ cmp x8, #0x2
+ b.lo 1f
+
+ mrs x8, sctlr_el2
+#ifdef __AARCH64EB__
+ orr x8, x8, #SCTLR_EE /* set: Big Endian */
+#else
+ bic x8, x8, #SCTLR_EE /* clear: Little Endian */
+#endif
+ msr sctlr_el2, x8
+ isb
+ b 2f
+
+1:
+ mrs x8, sctlr_el1
+#ifdef __AARCH64EB__
+ orr x8, x8, #SCTLR_EE /* set: Big Endian */
+#else
+ bic x8, x8, #SCTLR_EE /* clear: Little Endian */
+#endif
+ msr sctlr_el1, x8
+ isb
+
+2:
adr x9, start
ldr x10, =start
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