[src/trunk]: src/sys/arch/mips/mips Octeon CN70XX CPUs have a COP0 config5 re...

[simonb <simonb%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/af4067bce435
branches:  trunk
changeset: 938090:af4067bce435
user:      simonb <simonb%NetBSD.org@localhost>
date:      Wed Sep 02 01:33:27 2020 +0000

description:
Octeon CN70XX CPUs have a COP0 config5 register.
XXX: The presense of these are defined by the MIPS architecture, should probe.

diffstat:

 sys/arch/mips/mips/mips_machdep.c |  12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diffs (33 lines):

diff -r df4d6500d28d -r af4067bce435 sys/arch/mips/mips/mips_machdep.c
--- a/sys/arch/mips/mips/mips_machdep.c Wed Sep 02 00:15:15 2020 +0000
+++ b/sys/arch/mips/mips/mips_machdep.c Wed Sep 02 01:33:27 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mips_machdep.c,v 1.299 2020/08/17 03:22:13 mrg Exp $   */
+/*     $NetBSD: mips_machdep.c,v 1.300 2020/09/02 01:33:27 simonb Exp $        */
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -111,7 +111,7 @@
  */
 
 #include <sys/cdefs.h>                 /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.299 2020/08/17 03:22:13 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.300 2020/09/02 01:33:27 simonb Exp $");
 
 #define __INTR_PRIVATE
 #include "opt_cputype.h"
@@ -672,10 +672,10 @@
 
        { MIPS_PRID_CID_CAVIUM, MIPS_CN70XX, -1, -1, -1, 0,
          MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR,
-         MIPS_CP0FL_USE |
-         MIPS_CP0FL_EBASE | MIPS_CP0FL_CONFIG |
-         MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 | MIPS_CP0FL_CONFIG3 |
-         MIPS_CP0FL_CONFIG4 | MIPS_CP0FL_CONFIG6 | MIPS_CP0FL_CONFIG7,
+         MIPS_CP0FL_USE | MIPS_CP0FL_EBASE |
+         MIPS_CP0FL_CONFIG  | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 |
+         MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG4 | MIPS_CP0FL_CONFIG5 |
+         MIPS_CP0FL_CONFIG6 | MIPS_CP0FL_CONFIG7,
          0,
          "CN70xx/CN71xx"       },