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[src/netbsd-8]: src/sys/arch/x86/x86 Pull up following revision(s) (requested...
details: https://anonhg.NetBSD.org/src/rev/85e8590f3e3c
branches: netbsd-8
changeset: 936820:85e8590f3e3c
user: martin <martin%NetBSD.org@localhost>
date: Wed Aug 05 16:05:49 2020 +0000
description:
Pull up following revision(s) (requested by msaitoh in ticket #1589):
sys/arch/x86/x86/coretemp.c: revision 1.37
Add special handling for model 0x0f stepping >=2 or mode 0x0e to get Tjmax.
diffstat:
sys/arch/x86/x86/coretemp.c | 18 ++++++++++++++++--
1 files changed, 16 insertions(+), 2 deletions(-)
diffs (46 lines):
diff -r 084987dd7879 -r 85e8590f3e3c sys/arch/x86/x86/coretemp.c
--- a/sys/arch/x86/x86/coretemp.c Wed Aug 05 16:02:53 2020 +0000
+++ b/sys/arch/x86/x86/coretemp.c Wed Aug 05 16:05:49 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: coretemp.c,v 1.35.10.1 2018/07/26 23:23:50 snj Exp $ */
+/* $NetBSD: coretemp.c,v 1.35.10.2 2020/08/05 16:05:49 martin Exp $ */
/*-
* Copyright (c) 2011 The NetBSD Foundation, Inc.
@@ -61,7 +61,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.35.10.1 2018/07/26 23:23:50 snj Exp $");
+__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.35.10.2 2020/08/05 16:05:49 martin Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -271,6 +271,19 @@
sc->sc_tjmax = 100;
if ((model == 0x0f && stepping >= 2) || (model == 0x0e)) {
+ /*
+ * Check MSR_IA32_PLATFORM_ID(0x17) bit 28. It's not documented
+ * in the datasheet, but the following page describes the
+ * detail:
+ * http://software.intel.com/en-us/articles/
+ * mobile-intel-core2-processor-detection-table/
+ * Was: http://softwarecommunity.intel.com/Wiki/Mobility/
+ * 720.htm
+ */
+ if (rdmsr_safe(MSR_IA32_PLATFORM_ID, &msr) != 0)
+ goto notee;
+ if ((model < 0x17) && ((msr & __BIT(28)) == 0))
+ goto notee;
if (rdmsr_safe(MSR_IA32_EXT_CONFIG, &msr) == EFAULT)
return;
@@ -290,6 +303,7 @@
} else
sc->sc_tjmax = 90;
} else {
+notee:
/*
* Attempt to get Tj(max) from IA32_TEMPERATURE_TARGET,
* but only consider the interval [70, 110] C as valid.
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