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[src/trunk]: src/sys/arch/mips/include #define<tab>
details: https://anonhg.NetBSD.org/src/rev/3cfac90002c4
branches: trunk
changeset: 936358:3cfac90002c4
user: simonb <simonb%NetBSD.org@localhost>
date: Sun Jul 26 08:08:41 2020 +0000
description:
#define<tab>
Nuke trailing whitespace.
diffstat:
sys/arch/mips/include/asm.h | 8 +-
sys/arch/mips/include/bswap.h | 4 +-
sys/arch/mips/include/bus_dma_defs.h | 8 +-
sys/arch/mips/include/bus_space_defs.h | 18 +-
sys/arch/mips/include/bus_space_funcs.h | 4 +-
sys/arch/mips/include/cache.h | 4 +-
sys/arch/mips/include/cache_ls2.h | 12 +-
sys/arch/mips/include/cache_mipsNN.h | 4 +-
sys/arch/mips/include/cache_octeon.h | 4 +-
sys/arch/mips/include/cache_r4k.h | 14 +-
sys/arch/mips/include/cache_r5900.h | 30 +-
sys/arch/mips/include/cache_r5k.h | 14 +-
sys/arch/mips/include/cachectl.h | 14 +-
sys/arch/mips/include/cdefs.h | 14 +-
sys/arch/mips/include/cpu.h | 42 +-
sys/arch/mips/include/cpu_counter.h | 8 +-
sys/arch/mips/include/cpuregs.h | 40 +-
sys/arch/mips/include/db_machdep.h | 16 +-
sys/arch/mips/include/ecoff_machdep.h | 32 +-
sys/arch/mips/include/fenv.h | 4 +-
sys/arch/mips/include/float.h | 8 +-
sys/arch/mips/include/frame.h | 6 +-
sys/arch/mips/include/ieeefp.h | 16 +-
sys/arch/mips/include/int_const.h | 4 +-
sys/arch/mips/include/int_fmtio.h | 4 +-
sys/arch/mips/include/int_limits.h | 6 +-
sys/arch/mips/include/int_mwgwtypes.h | 4 +-
sys/arch/mips/include/intr.h | 8 +-
sys/arch/mips/include/isa_machdep.h | 8 +-
sys/arch/mips/include/kcore.h | 4 +-
sys/arch/mips/include/kdbparam.h | 8 +-
sys/arch/mips/include/limits.h | 20 +-
sys/arch/mips/include/locore.h | 158 +++++-----
sys/arch/mips/include/math.h | 4 +-
sys/arch/mips/include/mcontext.h | 104 +++---
sys/arch/mips/include/mips1_pte.h | 14 +-
sys/arch/mips/include/mips3_pte.h | 38 +-
sys/arch/mips/include/mipsNN.h | 122 ++++----
sys/arch/mips/include/mips_opcode.h | 416 +++++++++++++++---------------
sys/arch/mips/include/mips_param.h | 22 +-
sys/arch/mips/include/netbsd32_machdep.h | 6 +-
sys/arch/mips/include/pci_machdep.h | 6 +-
sys/arch/mips/include/pmap.h | 38 +-
sys/arch/mips/include/proc.h | 4 +-
sys/arch/mips/include/profile.h | 4 +-
sys/arch/mips/include/pte.h | 10 +-
sys/arch/mips/include/ptrace.h | 26 +-
sys/arch/mips/include/r3900regs.h | 114 ++++----
sys/arch/mips/include/reg.h | 4 +-
sys/arch/mips/include/regdef.h | 68 ++--
sys/arch/mips/include/regnum.h | 170 ++++++------
sys/arch/mips/include/reloc.h | 6 +-
sys/arch/mips/include/setjmp.h | 4 +-
sys/arch/mips/include/sljit_machdep.h | 12 +-
sys/arch/mips/include/sysarch.h | 8 +-
sys/arch/mips/include/vmparam.h | 52 +-
sys/arch/mips/include/wchar_limits.h | 4 +-
sys/arch/mips/include/wired_map.h | 14 +-
58 files changed, 909 insertions(+), 909 deletions(-)
diffs (truncated from 3587 to 300 lines):
diff -r 986999a4d660 -r 3cfac90002c4 sys/arch/mips/include/asm.h
--- a/sys/arch/mips/include/asm.h Sun Jul 26 07:57:06 2020 +0000
+++ b/sys/arch/mips/include/asm.h Sun Jul 26 08:08:41 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: asm.h,v 1.56 2020/04/17 14:19:43 joerg Exp $ */
+/* $NetBSD: asm.h,v 1.57 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -267,7 +267,7 @@
.asciz str; \
.align 3
-#define RCSID(x) .pushsection ".ident","MS",@progbits,1; \
+#define RCSID(x) .pushsection ".ident","MS",@progbits,1; \
.asciz x; \
.popsection
@@ -515,9 +515,9 @@
/* CPU dependent hook for cp0 load delays */
#if defined(MIPS1) || defined(MIPS2) || defined(MIPS3)
-#define MFC0_HAZARD sll $0,$0,1 /* super scalar nop */
+#define MFC0_HAZARD sll $0,$0,1 /* super scalar nop */
#else
-#define MFC0_HAZARD /* nothing */
+#define MFC0_HAZARD /* nothing */
#endif
#if _MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || \
diff -r 986999a4d660 -r 3cfac90002c4 sys/arch/mips/include/bswap.h
--- a/sys/arch/mips/include/bswap.h Sun Jul 26 07:57:06 2020 +0000
+++ b/sys/arch/mips/include/bswap.h Sun Jul 26 08:08:41 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: bswap.h,v 1.4 2013/05/23 21:39:49 christos Exp $ */
+/* $NetBSD: bswap.h,v 1.5 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -28,7 +28,7 @@
#ifndef _MIPS_BSWAP_H_
#define _MIPS_BSWAP_H_
-#define __BSWAP_RENAME
+#define __BSWAP_RENAME
#include <sys/bswap.h>
#endif /* !_MIPS_BSWAP_H_ */
diff -r 986999a4d660 -r 3cfac90002c4 sys/arch/mips/include/bus_dma_defs.h
--- a/sys/arch/mips/include/bus_dma_defs.h Sun Jul 26 07:57:06 2020 +0000
+++ b/sys/arch/mips/include/bus_dma_defs.h Sun Jul 26 08:08:41 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_dma_defs.h,v 1.4 2019/02/07 04:32:54 mrg Exp $ */
+/* $NetBSD: bus_dma_defs.h,v 1.5 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 1997, 1998, 2000, 2001 The NetBSD Foundation, Inc.
@@ -82,7 +82,7 @@
#define BUS_DMA_READ 0x100 /* mapping is device -> memory only */
#define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */
#define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */
-#define BUS_DMA_PREFETCHABLE 0x800 /* hint: map non-cached but allow
+#define BUS_DMA_PREFETCHABLE 0x800 /* hint: map non-cached but allow
* things like write combining */
/*
@@ -278,7 +278,7 @@
.dmamap_sync = _bus_dmamap_sync, \
}
-#define _BUS_DMAMEM_OPS_INITIALIZER { \
+#define _BUS_DMAMEM_OPS_INITIALIZER { \
.dmamem_alloc = _bus_dmamem_alloc, \
.dmamem_free = _bus_dmamem_free, \
.dmamem_map = _bus_dmamem_map, \
@@ -286,7 +286,7 @@
.dmamem_mmap = _bus_dmamem_mmap, \
}
-#define _BUS_DMATAG_OPS_INITIALIZER { \
+#define _BUS_DMATAG_OPS_INITIALIZER { \
.dmatag_subregion = _bus_dmatag_subregion, \
.dmatag_destroy = _bus_dmatag_destroy, \
}
diff -r 986999a4d660 -r 3cfac90002c4 sys/arch/mips/include/bus_space_defs.h
--- a/sys/arch/mips/include/bus_space_defs.h Sun Jul 26 07:57:06 2020 +0000
+++ b/sys/arch/mips/include/bus_space_defs.h Sun Jul 26 08:08:41 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space_defs.h,v 1.3 2016/09/15 21:45:37 jdolecek Exp $ */
+/* $NetBSD: bus_space_defs.h,v 1.4 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 1997, 1998, 2000, 2001 The NetBSD Foundation, Inc.
@@ -95,10 +95,10 @@
(void) 0; \
})
-#define BUS_SPACE_ALIGNED_POINTER(p, t) __BUS_SPACE_ALIGNED_ADDRESS(p, t)
+#define BUS_SPACE_ALIGNED_POINTER(p, t) __BUS_SPACE_ALIGNED_ADDRESS(p, t)
#else
#define __BUS_SPACE_ADDRESS_SANITY(p, t, d) (void) 0
-#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
+#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
#endif /* BUS_SPACE_DEBUG */
#endif /* _KERNEL */
@@ -184,7 +184,7 @@
uint32_t *, bus_size_t);
void (*bs_rm_8)(void *, bus_space_handle_t, bus_size_t,
uint64_t *, bus_size_t);
-
+
/* read region */
void (*bs_rr_1)(void *, bus_space_handle_t, bus_size_t,
uint8_t *, bus_size_t);
@@ -194,7 +194,7 @@
uint32_t *, bus_size_t);
void (*bs_rr_8)(void *, bus_space_handle_t, bus_size_t,
uint64_t *, bus_size_t);
-
+
/* write (single) */
void (*bs_w_1)(void *, bus_space_handle_t, bus_size_t,
uint8_t);
@@ -214,7 +214,7 @@
const uint32_t *, bus_size_t);
void (*bs_wm_8)(void *, bus_space_handle_t, bus_size_t,
const uint64_t *, bus_size_t);
-
+
/* write region */
void (*bs_wr_1)(void *, bus_space_handle_t, bus_size_t,
const uint8_t *, bus_size_t);
@@ -240,7 +240,7 @@
uint32_t *, bus_size_t);
void (*bs_rms_8)(void *, bus_space_handle_t, bus_size_t,
uint64_t *, bus_size_t);
-
+
/* read region stream */
void (*bs_rrs_1)(void *, bus_space_handle_t, bus_size_t,
uint8_t *, bus_size_t);
@@ -250,7 +250,7 @@
uint32_t *, bus_size_t);
void (*bs_rrs_8)(void *, bus_space_handle_t, bus_size_t,
uint64_t *, bus_size_t);
-
+
/* write (single) stream */
void (*bs_ws_1)(void *, bus_space_handle_t, bus_size_t,
uint8_t);
@@ -270,7 +270,7 @@
const uint32_t *, bus_size_t);
void (*bs_wms_8)(void *, bus_space_handle_t, bus_size_t,
const uint64_t *, bus_size_t);
-
+
/* write region stream */
void (*bs_wrs_1)(void *, bus_space_handle_t, bus_size_t,
const uint8_t *, bus_size_t);
diff -r 986999a4d660 -r 3cfac90002c4 sys/arch/mips/include/bus_space_funcs.h
--- a/sys/arch/mips/include/bus_space_funcs.h Sun Jul 26 07:57:06 2020 +0000
+++ b/sys/arch/mips/include/bus_space_funcs.h Sun Jul 26 08:08:41 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space_funcs.h,v 1.1 2011/07/01 17:28:55 dyoung Exp $ */
+/* $NetBSD: bus_space_funcs.h,v 1.2 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 1997, 1998, 2000, 2001 The NetBSD Foundation, Inc.
@@ -129,7 +129,7 @@
/*
* Get kernel virtual address for ranges mapped BUS_SPACE_MAP_LINEAR.
*/
-#define bus_space_vaddr(t, h) \
+#define bus_space_vaddr(t, h) \
(*(t)->bs_vaddr)((t)->bs_cookie, (h))
/*
diff -r 986999a4d660 -r 3cfac90002c4 sys/arch/mips/include/cache.h
--- a/sys/arch/mips/include/cache.h Sun Jul 26 07:57:06 2020 +0000
+++ b/sys/arch/mips/include/cache.h Sun Jul 26 08:08:41 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.h,v 1.14 2016/08/18 22:23:20 skrll Exp $ */
+/* $NetBSD: cache.h,v 1.15 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
*/
#ifndef _MIPS_CACHE_H_
-#define _MIPS_CACHE_H_
+#define _MIPS_CACHE_H_
/*
* Cache operations.
diff -r 986999a4d660 -r 3cfac90002c4 sys/arch/mips/include/cache_ls2.h
--- a/sys/arch/mips/include/cache_ls2.h Sun Jul 26 07:57:06 2020 +0000
+++ b/sys/arch/mips/include/cache_ls2.h Sun Jul 26 08:08:41 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_ls2.h,v 1.3 2016/07/11 16:15:35 matt Exp $ */
+/* $NetBSD: cache_ls2.h,v 1.4 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#ifndef _MIPS_CACHE_LS2_H_
-#define _MIPS_CACHE_LS2_H_
+#define _MIPS_CACHE_LS2_H_
/*
* Cache definitions/operations for Loongson-style caches.
@@ -48,7 +48,7 @@
* The way is encoded in the bottom 2 bits of VA.
*/
-#define cache_op_ls2_8line_4way(va, op) \
+#define cache_op_ls2_8line_4way(va, op) \
__asm volatile( \
".set noreorder \n\t" \
"cache %1, 0x00(%0); cache %1, 0x20(%0) \n\t" \
@@ -72,7 +72,7 @@
: "r" (va), "i" (op) \
: "memory");
-#define cache_op_ls2_line_4way(va, op) \
+#define cache_op_ls2_line_4way(va, op) \
__asm volatile( \
".set noreorder \n\t" \
"cache %1, 0(%0); cache %1, 1(%0) \n\t" \
@@ -82,7 +82,7 @@
: "r" (va), "i" (op) \
: "memory");
-#define cache_op_ls2_8line(va, op) \
+#define cache_op_ls2_8line(va, op) \
__asm volatile( \
".set noreorder \n\t" \
"cache %1, 0x00(%0); cache %1, 0x20(%0) \n\t" \
@@ -94,7 +94,7 @@
: "r" (va), "i" (op) \
: "memory");
-#define cache_op_ls2_line(va, op) \
+#define cache_op_ls2_line(va, op) \
__asm volatile( \
".set noreorder \n\t" \
"cache %1, 0(%0) \n\t" \
diff -r 986999a4d660 -r 3cfac90002c4 sys/arch/mips/include/cache_mipsNN.h
--- a/sys/arch/mips/include/cache_mipsNN.h Sun Jul 26 07:57:06 2020 +0000
+++ b/sys/arch/mips/include/cache_mipsNN.h Sun Jul 26 08:08:41 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_mipsNN.h,v 1.5 2016/07/11 16:15:35 matt Exp $ */
+/* $NetBSD: cache_mipsNN.h,v 1.6 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
*/
#ifndef _MIPS_CACHE_MIPSNN_H_
-#define _MIPS_CACHE_MIPSNN_H_
+#define _MIPS_CACHE_MIPSNN_H_
void mipsNN_cache_init(uint32_t, uint32_t);
diff -r 986999a4d660 -r 3cfac90002c4 sys/arch/mips/include/cache_octeon.h
--- a/sys/arch/mips/include/cache_octeon.h Sun Jul 26 07:57:06 2020 +0000
+++ b/sys/arch/mips/include/cache_octeon.h Sun Jul 26 08:08:41 2020 +0000
@@ -1,7 +1,7 @@
-/* $NetBSD: cache_octeon.h,v 1.4 2020/06/14 08:43:07 simonb Exp $ */
+/* $NetBSD: cache_octeon.h,v 1.5 2020/07/26 08:08:41 simonb Exp $ */
#ifndef _MIPS_CACHE_OCTEON_H_
-#define _MIPS_CACHE_OCTEON_H_
+#define _MIPS_CACHE_OCTEON_H_
#define CACHE_OCTEON_I 0
#define CACHE_OCTEON_D 1
diff -r 986999a4d660 -r 3cfac90002c4 sys/arch/mips/include/cache_r4k.h
--- a/sys/arch/mips/include/cache_r4k.h Sun Jul 26 07:57:06 2020 +0000
+++ b/sys/arch/mips/include/cache_r4k.h Sun Jul 26 08:08:41 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_r4k.h,v 1.16 2016/07/12 15:56:23 skrll Exp $ */
+/* $NetBSD: cache_r4k.h,v 1.17 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -63,7 +63,7 @@
*
* Perform the specified cache operation on a single line.
*/
-#define cache_op_r4k_line(va, op) \
+#define cache_op_r4k_line(va, op) \
{ \
__asm volatile( \
".set push" "\n\t" \
@@ -120,7 +120,7 @@
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