[src/netbsd-8]: src/sys/dev/mii regen for ticket #1577

[martin <martin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/819e977e4c35
branches:  netbsd-8
changeset: 936192:819e977e4c35
user:      martin <martin%NetBSD.org@localhost>
date:      Mon Jul 20 18:43:25 2020 +0000

description:
regen for ticket #1577

diffstat:

 sys/dev/mii/miidevs.h      |  24 ++++++++++++++++++++++--
 sys/dev/mii/miidevs_data.h |  14 ++++++++++++--
 2 files changed, 34 insertions(+), 4 deletions(-)

diffs (79 lines):

diff -r fd584ea49241 -r 819e977e4c35 sys/dev/mii/miidevs.h
--- a/sys/dev/mii/miidevs.h     Mon Jul 20 18:42:47 2020 +0000
+++ b/sys/dev/mii/miidevs.h     Mon Jul 20 18:43:25 2020 +0000
@@ -1,10 +1,10 @@
-/*     $NetBSD: miidevs.h,v 1.128.6.9 2020/04/14 18:11:35 martin Exp $ */
+/*     $NetBSD: miidevs.h,v 1.128.6.10 2020/07/20 18:43:25 martin Exp $        */
 
 /*
  * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
  *
  * generated from:
- *     NetBSD: miidevs,v 1.125.6.9 2020/04/14 17:57:17 martin Exp
+ *     NetBSD: miidevs,v 1.125.6.10 2020/07/20 18:42:47 martin Exp
  */
 
 /*-
@@ -616,8 +616,28 @@
 #define        MII_STR_xxVITESSE_VSC8601       "VSC8601 10/100/1000 PHY"
 #define        MII_MODEL_xxVITESSE_VSC8641     0x0003
 #define        MII_STR_xxVITESSE_VSC8641       "Vitesse VSC8641 10/100/1000TX PHY"
+#define        MII_MODEL_xxVITESSE_VSC8504     0x000c
+#define        MII_STR_xxVITESSE_VSC8504       "Vitesse VSC8504 quad 10/100/1000TX PHY"
+#define        MII_MODEL_xxVITESSE_VSC8552     0x000e
+#define        MII_STR_xxVITESSE_VSC8552       "Vitesse VSC8552 dual 10/100/1000TX PHY"
+#define        MII_MODEL_xxVITESSE_VSC8502     0x0012
+#define        MII_STR_xxVITESSE_VSC8502       "Vitesse VSC8502 dual 10/100/1000TX PHY"
 #define        MII_MODEL_xxVITESSE_VSC8501     0x0013
 #define        MII_STR_xxVITESSE_VSC8501       "Vitesse VSC8501 10/100/1000TX PHY"
+#define        MII_MODEL_xxVITESSE_VSC8531     0x0017
+#define        MII_STR_xxVITESSE_VSC8531       "Vitesse VSC8531 10/100/1000TX PHY"
+#define        MII_MODEL_xxVITESSE_VSC8662     0x0026
+#define        MII_STR_xxVITESSE_VSC8662       "Vitesse VSC866[24] dual/quad 1000T 100FX 1000X PHY"
+#define        MII_MODEL_xxVITESSE_VSC8514     0x0027
+#define        MII_STR_xxVITESSE_VSC8514       "Vitesse VSC8514 quad 1000T PHY"
+#define        MII_MODEL_xxVITESSE_VSC8512     0x002e
+#define        MII_STR_xxVITESSE_VSC8512       "Vitesse VSC8512 12port 1000T PHY"
+#define        MII_MODEL_xxVITESSE_VSC8522     0x002f
+#define        MII_STR_xxVITESSE_VSC8522       "Vitesse VSC8522 12port 1000T PHY"
+#define        MII_MODEL_xxVITESSE_VSC8658     0x0035
+#define        MII_STR_xxVITESSE_VSC8658       "Vitesse VSC8658 octal 1000T 100FX 1000X PHY"
+#define        MII_MODEL_xxVITESSE_VSC8541     0x0037
+#define        MII_STR_xxVITESSE_VSC8541       "Vitesse VSC8541 1000T PHY"
 
 /* XaQti Corp. PHYs */
 #define        MII_MODEL_xxXAQTI_XMACII        0x0000
diff -r fd584ea49241 -r 819e977e4c35 sys/dev/mii/miidevs_data.h
--- a/sys/dev/mii/miidevs_data.h        Mon Jul 20 18:42:47 2020 +0000
+++ b/sys/dev/mii/miidevs_data.h        Mon Jul 20 18:43:25 2020 +0000
@@ -1,10 +1,10 @@
-/*     $NetBSD: miidevs_data.h,v 1.116.6.9 2020/04/14 18:11:35 martin Exp $    */
+/*     $NetBSD: miidevs_data.h,v 1.116.6.10 2020/07/20 18:43:25 martin Exp $   */
 
 /*
  * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
  *
  * generated from:
- *     NetBSD: miidevs,v 1.125.6.9 2020/04/14 17:57:17 martin Exp
+ *     NetBSD: miidevs,v 1.125.6.10 2020/07/20 18:42:47 martin Exp
  */
 
 /*-
@@ -246,7 +246,17 @@
  { MII_OUI_xxVIA, MII_MODEL_xxVIA_VT6103_2, MII_STR_xxVIA_VT6103_2 },
  { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8601, MII_STR_xxVITESSE_VSC8601 },
  { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8641, MII_STR_xxVITESSE_VSC8641 },
+ { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8504, MII_STR_xxVITESSE_VSC8504 },
+ { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8552, MII_STR_xxVITESSE_VSC8552 },
+ { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8502, MII_STR_xxVITESSE_VSC8502 },
  { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8501, MII_STR_xxVITESSE_VSC8501 },
+ { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8531, MII_STR_xxVITESSE_VSC8531 },
+ { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8662, MII_STR_xxVITESSE_VSC8662 },
+ { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8514, MII_STR_xxVITESSE_VSC8514 },
+ { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8512, MII_STR_xxVITESSE_VSC8512 },
+ { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8522, MII_STR_xxVITESSE_VSC8522 },
+ { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8658, MII_STR_xxVITESSE_VSC8658 },
+ { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8541, MII_STR_xxVITESSE_VSC8541 },
  { MII_OUI_xxXAQTI, MII_MODEL_xxXAQTI_XMACII, MII_STR_xxXAQTI_XMACII },
  { 0, 0, NULL }
 };