[src/trunk]: src/sys/arch/aarch64 Draft fpu_kern_enter/leave on aarch64.

[riastradh <riastradh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/a132c220d177
branches:  trunk
changeset: 935299:a132c220d177
user:      riastradh <riastradh%NetBSD.org@localhost>
date:      Mon Jun 29 23:22:27 2020 +0000

description:
Draft fpu_kern_enter/leave on aarch64.

diffstat:

 sys/arch/aarch64/aarch64/cpu.c     |   6 ++-
 sys/arch/aarch64/aarch64/fpu.c     |  71 ++++++++++++++++++++++++++++++++++++-
 sys/arch/aarch64/include/cpu.h     |   4 +-
 sys/arch/aarch64/include/fpu.h     |  35 ++++++++++++++++++
 sys/arch/aarch64/include/machdep.h |   4 +-
 5 files changed, 113 insertions(+), 7 deletions(-)

diffs (197 lines):

diff -r 40e1cf230112 -r a132c220d177 sys/arch/aarch64/aarch64/cpu.c
--- a/sys/arch/aarch64/aarch64/cpu.c    Mon Jun 29 23:04:56 2020 +0000
+++ b/sys/arch/aarch64/aarch64/cpu.c    Mon Jun 29 23:22:27 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.47 2020/06/14 16:10:18 riastradh Exp $ */
+/* $NetBSD: cpu.c,v 1.48 2020/06/29 23:22:27 riastradh Exp $ */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.47 2020/06/14 16:10:18 riastradh Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.48 2020/06/29 23:22:27 riastradh Exp $");
 
 #include "locators.h"
 #include "opt_arm_debug.h"
@@ -133,6 +133,8 @@
        ci->ci_dev = dv;
        dv->dv_private = ci;
 
+       ci->ci_kfpu_spl = -1;
+
        arm_cpu_do_topology(ci);
        cpu_identify(ci->ci_dev, ci);
 
diff -r 40e1cf230112 -r a132c220d177 sys/arch/aarch64/aarch64/fpu.c
--- a/sys/arch/aarch64/aarch64/fpu.c    Mon Jun 29 23:04:56 2020 +0000
+++ b/sys/arch/aarch64/aarch64/fpu.c    Mon Jun 29 23:22:27 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: fpu.c,v 1.3 2018/11/07 06:47:38 riastradh Exp $ */
+/* $NetBSD: fpu.c,v 1.4 2020/06/29 23:22:27 riastradh Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,13 +31,15 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: fpu.c,v 1.3 2018/11/07 06:47:38 riastradh Exp $");
+__KERNEL_RCSID(1, "$NetBSD: fpu.c,v 1.4 2020/06/29 23:22:27 riastradh Exp $");
 
 #include <sys/param.h>
 #include <sys/types.h>
 #include <sys/lwp.h>
 #include <sys/evcnt.h>
 
+#include <aarch64/fpu.h>
+#include <aarch64/locore.h>
 #include <aarch64/reg.h>
 #include <aarch64/pcb.h>
 #include <aarch64/armreg.h>
@@ -172,3 +174,68 @@
        reg_cpacr_el1_write(CPACR_FPEN_NONE);
        __asm __volatile ("isb");
 }
+
+void
+fpu_kern_enter(void)
+{
+       struct lwp *l = curlwp;
+       struct cpu_info *ci;
+       int s;
+
+       /*
+        * Block all interrupts.  We must block preemption since -- if
+        * this is a user thread -- there is nowhere to save the kernel
+        * fpu state, and if we want this to be usable in interrupts,
+        * we can't let interrupts interfere with the fpu state in use
+        * since there's nowhere for them to save it.
+        */
+       s = splhigh();
+       ci = curcpu();
+       KASSERT(ci->ci_kfpu_spl == -1);
+       ci->ci_kfpu_spl = s;
+
+       /*
+        * If we are in a softint and have a pinned lwp, the fpu state
+        * is that of the pinned lwp, so save it there.
+        */
+       if ((l->l_pflag & LP_INTR) && (l->l_switchto != NULL))
+               l = l->l_switchto;
+       if (fpu_used_p(l))
+               fpu_save(l);
+
+       /*
+        * Enable the fpu, and wait until it is enabled before
+        * executing any further instructions.
+        */
+       reg_cpacr_el1_write(CPACR_FPEN_ALL);
+       arm_isb();
+}
+
+void
+fpu_kern_leave(void)
+{
+       static const struct fpreg zero_fpreg;
+       struct cpu_info *ci = curcpu();
+       int s;
+
+       KASSERT(ci->ci_cpl == IPL_HIGH);
+       KASSERT(ci->ci_kfpu_spl != -1);
+
+       /*
+        * Zero the fpu registers; otherwise we might leak secrets
+        * through Spectre-class attacks to userland, even if there are
+        * no bugs in fpu state management.
+        */
+       load_fpregs(&zero_fpreg);
+
+       /*
+        * Disable the fpu so that the kernel can't accidentally use
+        * it again.
+        */
+       reg_cpacr_el1_write(CPACR_FPEN_NONE);
+       arm_isb();
+
+       s = ci->ci_kfpu_spl;
+       ci->ci_kfpu_spl = -1;
+       splx(s);
+}
diff -r 40e1cf230112 -r a132c220d177 sys/arch/aarch64/include/cpu.h
--- a/sys/arch/aarch64/include/cpu.h    Mon Jun 29 23:04:56 2020 +0000
+++ b/sys/arch/aarch64/include/cpu.h    Mon Jun 29 23:22:27 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.22 2020/03/10 01:17:33 christos Exp $ */
+/* $NetBSD: cpu.h,v 1.23 2020/06/29 23:22:27 riastradh Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -89,6 +89,8 @@
        volatile u_int ci_astpending;
        volatile u_int ci_intr_depth;
 
+       int ci_kfpu_spl;
+
        /* event counters */
        struct evcnt ci_vfp_use;
        struct evcnt ci_vfp_reuse;
diff -r 40e1cf230112 -r a132c220d177 sys/arch/aarch64/include/fpu.h
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/aarch64/include/fpu.h    Mon Jun 29 23:22:27 2020 +0000
@@ -0,0 +1,35 @@
+/*     $NetBSD: fpu.h,v 1.1 2020/06/29 23:22:27 riastradh Exp $        */
+
+/*
+ * Copyright (c) 2020 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _AARCH64_FPU_H_
+#define _AARCH64_FPU_H_
+
+void fpu_kern_enter(void);
+void fpu_kern_leave(void);
+
+#endif /* _AARCH64_FPU_H_ */
diff -r 40e1cf230112 -r a132c220d177 sys/arch/aarch64/include/machdep.h
--- a/sys/arch/aarch64/include/machdep.h        Mon Jun 29 23:04:56 2020 +0000
+++ b/sys/arch/aarch64/include/machdep.h        Mon Jun 29 23:22:27 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: machdep.h,v 1.11 2020/05/23 18:08:59 ryo Exp $ */
+/*     $NetBSD: machdep.h,v 1.12 2020/06/29 23:22:27 riastradh Exp $   */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -142,7 +142,7 @@
 /* fpu.c */
 void fpu_attach(struct cpu_info *);
 struct fpreg;
-void load_fpregs(struct fpreg *);
+void load_fpregs(const struct fpreg *);
 void save_fpregs(struct fpreg *);
 
 #ifdef TRAP_SIGDEBUG