[src/trunk]: src/sys/arch/aarch64/aarch64 no need to make the PTE writable to...

[ryo <ryo%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/b90f5cae2cbc
branches:  trunk
changeset: 933958:b90f5cae2cbc
user:      ryo <ryo%NetBSD.org@localhost>
date:      Mon Jun 01 02:42:24 2020 +0000

description:
no need to make the PTE writable to do icache_sync, enough to accessible.

diffstat:

 sys/arch/aarch64/aarch64/pmap.c |  18 +++++++-----------
 1 files changed, 7 insertions(+), 11 deletions(-)

diffs (57 lines):

diff -r 94e39edf8c1b -r b90f5cae2cbc sys/arch/aarch64/aarch64/pmap.c
--- a/sys/arch/aarch64/aarch64/pmap.c   Mon Jun 01 01:41:40 2020 +0000
+++ b/sys/arch/aarch64/aarch64/pmap.c   Mon Jun 01 02:42:24 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.c,v 1.75 2020/05/15 05:39:15 skrll Exp $  */
+/*     $NetBSD: pmap.c,v 1.76 2020/06/01 02:42:24 ryo Exp $    */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.75 2020/05/15 05:39:15 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.76 2020/06/01 02:42:24 ryo Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
@@ -171,17 +171,13 @@
        } while (0/*CONSTCOND*/)
 
 /*
- * aarch64 require write permission in pte to invalidate instruction cache.
- * changing pte to writable temporarly before cpu_icache_sync_range().
+ * require access permission in pte to invalidate instruction cache.
+ * change the pte to accessible temporarly before cpu_icache_sync_range().
  * this macro modifies PTE (*ptep). need to update PTE after this.
  */
 #define PTE_ICACHE_SYNC_PAGE(pte, ptep, pm, va, ll)                    \
        do {                                                            \
-               pt_entry_t tpte;                                        \
-               tpte = (pte) & ~(LX_BLKPAG_AF|LX_BLKPAG_AP);            \
-               tpte |= (LX_BLKPAG_AF|LX_BLKPAG_AP_RW);                 \
-               tpte |= (LX_BLKPAG_UXN|LX_BLKPAG_PXN);                  \
-               atomic_swap_64((ptep), tpte);                           \
+               atomic_swap_64((ptep), (pte) | LX_BLKPAG_AF);           \
                AARCH64_TLBI_BY_ASID_VA((pm)->pm_asid, (va), (ll));     \
                cpu_icache_sync_range((va), PAGE_SIZE);                 \
        } while (0/*CONSTCOND*/)
@@ -1328,7 +1324,7 @@
                        UVMHIST_LOG(pmaphist, "icache_sync: "
                            "pm=%p, va=%016lx, pte: %016lx -> %016lx",
                            pm, va, opte, pte);
-                       if (!l3pte_writable(pte)) {
+                       if (!l3pte_readable(pte)) {
                                PTE_ICACHE_SYNC_PAGE(pte, ptep, pm, va, true);
                                atomic_swap_64(ptep, pte);
                                AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, true);
@@ -1889,7 +1885,7 @@
                UVMHIST_LOG(pmaphist,
                    "icache_sync: pm=%p, va=%016lx, pte: %016lx -> %016lx",
                    pm, va, opte, pte);
-               if (!l3pte_writable(pte)) {
+               if (!l3pte_readable(pte)) {
                        PTE_ICACHE_SYNC_PAGE(pte, ptep, pm, va, l3only);
                        atomic_swap_64(ptep, pte);
                        AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va ,true);