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[src/trunk]: src/sys/dev/pci Fix all the random __SHIFTOUT casts by introduci...
details: https://anonhg.NetBSD.org/src/rev/876e7f215587
branches: trunk
changeset: 930629:876e7f215587
user: christos <christos%NetBSD.org@localhost>
date: Fri Apr 10 18:32:00 2020 +0000
description:
Fix all the random __SHIFTOUT casts by introducing an intermediate macho,
and then deleting and fixing the rest.
diffstat:
sys/dev/pci/pci_subr.c | 359 ++++++++++++++++++++++++------------------------
1 files changed, 180 insertions(+), 179 deletions(-)
diffs (truncated from 1133 to 300 lines):
diff -r bbba9e5ddac1 -r 876e7f215587 sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c Fri Apr 10 18:23:22 2020 +0000
+++ b/sys/dev/pci/pci_subr.c Fri Apr 10 18:32:00 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.222 2020/03/21 17:09:29 thorpej Exp $ */
+/* $NetBSD: pci_subr.c,v 1.223 2020/04/10 18:32:00 christos Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.222 2020/03/21 17:09:29 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.223 2020/04/10 18:32:00 christos Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -73,6 +73,7 @@
static int pci_conf_find_cap(const pcireg_t *, unsigned int, int *);
static int pci_conf_find_extcap(const pcireg_t *, unsigned int, int *);
static void pci_conf_print_pcie_power(uint8_t, unsigned int);
+#define PCIREG_SHIFTOUT(a, b) ((pcireg_t)__SHIFTOUT((a), (b)))
/*
* Descriptions of known PCI classes and subclasses.
@@ -721,7 +722,8 @@
#define i2o(i) ((i) * 4)
#define o2i(o) ((o) / 4)
-#define onoff2(str, rval, bit, onstr, offstr) \
+#define onoff2(str, rval, bit, onstr, offstr) \
+ /*CONSTCOND*/ \
printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr);
#define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off")
@@ -806,7 +808,7 @@
printf("unknown/reserved"); /* XXX */
break;
}
- printf(" (0x%x)\n", __SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK));
+ printf(" (0x%x)\n", PCIREG_SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK));
onoff("Slave signaled Target Abort", rval,
PCI_STATUS_TARGET_TARGET_ABORT);
@@ -1101,12 +1103,12 @@
rval = regs[o2i(capoff + PCI_AGP_STATUS)];
printf(" Status register: 0x%04x\n", rval);
- printf(" RQ: %d\n",
- (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1);
- printf(" ARQSZ: %d\n",
- (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ));
+ printf(" RQ: %u\n",
+ PCIREG_SHIFTOUT(rval, AGP_MODE_RQ) + 1);
+ printf(" ARQSZ: %u\n",
+ PCIREG_SHIFTOUT(rval, AGP_MODE_ARQSZ));
printf(" CAL cycle: %s\n",
- pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL)));
+ pci_conf_print_agp_calcycle(PCIREG_SHIFTOUT(rval, AGP_MODE_CAL)));
onoff("SBA", rval, AGP_MODE_SBA);
onoff("htrans#", rval, AGP_MODE_HTRANS);
onoff("Over 4G", rval, AGP_MODE_4G);
@@ -1118,12 +1120,12 @@
rval = regs[o2i(capoff + PCI_AGP_COMMAND)];
printf(" Command register: 0x%08x\n", rval);
- printf(" PRQ: %d\n",
- (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1);
- printf(" PARQSZ: %d\n",
- (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ));
+ printf(" PRQ: %u\n",
+ PCIREG_SHIFTOUT(rval, AGP_MODE_RQ) + 1);
+ printf(" PARQSZ: %u\n",
+ PCIREG_SHIFTOUT(rval, AGP_MODE_ARQSZ));
printf(" PCAL cycle: %s\n",
- pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL)));
+ pci_conf_print_agp_calcycle(PCIREG_SHIFTOUT(rval, AGP_MODE_CAL)));
onoff("SBA", rval, AGP_MODE_SBA);
onoff("AGP", rval, AGP_MODE_AGP);
onoff("Over 4G", rval, AGP_MODE_4G);
@@ -1200,16 +1202,16 @@
printf(" PME# assertion: %sabled\n",
(pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis");
printf(" Data Select: %d\n",
- __SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK));
+ PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK));
printf(" Data Scale: %d\n",
- __SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK));
+ PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK));
onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS);
printf(" Bridge Support Extensions register: 0x%02x\n",
(pmcsr >> 16) & 0xff);
onoff("B2/B3 support", pmcsr, PCI_PMCSR_B2B3_SUPPORT);
onoff("Bus Power/Clock Control Enable", pmcsr, PCI_PMCSR_BPCC_EN);
printf(" Data register: 0x%02x\n",
- __SHIFTOUT(pmcsr, PCI_PMCSR_DATA));
+ PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATA));
}
/* XXX pci_conf_print_vpd_cap */
@@ -1222,8 +1224,8 @@
regs += o2i(capoff);
ctl = *regs++;
- mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK);
- mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK);
+ mmc = PCIREG_SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK);
+ mme = PCIREG_SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK);
printf("\n PCI Message Signaled Interrupt\n");
@@ -1333,7 +1335,7 @@
onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN);
onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL);
pci_conf_print_pcix_cap_2ndbusmode(
- __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF));
+ PCIREG_SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF));
printf(" Version: 0x%x\n",
(reg & PCIX_BRIDGE_2NDST_VER_MASK)
>> PCIX_BRIDGE_2NDST_VER_SHIFT);
@@ -1537,7 +1539,7 @@
printf("\n Secure Capability Register\n");
reg = regs[o2i(capoff + PCI_SECURE_CAP)];
printf(" Capability Register: 0x%04x\n", reg >> 16);
- val = __SHIFTOUT(reg, PCI_SECURE_CAP_TYPE);
+ val = PCIREG_SHIFTOUT(reg, PCI_SECURE_CAP_TYPE);
printf(" Capability block type: ");
/* I know IOMMU Only */
if (val == PCI_SECURE_CAP_TYPE_IOMMU)
@@ -1547,7 +1549,7 @@
return;
}
- val = __SHIFTOUT(reg, PCI_SECURE_CAP_REV);
+ val = PCIREG_SHIFTOUT(reg, PCI_SECURE_CAP_REV);
printf(" Capability revision: 0x%02x ", val);
if (val == PCI_SECURE_CAP_REV_IOMMU)
printf("(IOMMU)\n");
@@ -1577,33 +1579,33 @@
reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)];
printf(" IOMMU Range Register: 0x%08x\n", reg);
printf(" HyperTransport UnitID: 0x%02x\n",
- (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_UNITID));
+ PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_UNITID));
onoff("Range valid", reg, PCI_SECURE_IOMMU_RANGE_RNGVALID);
printf(" Device range bus number: 0x%02x\n",
- (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_BUSNUM));
+ PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_BUSNUM));
printf(" First device: 0x%04x\n",
- (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_FIRSTDEV));
+ PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_FIRSTDEV));
printf(" Last device: 0x%04x\n",
- (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_LASTDEV));
+ PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_LASTDEV));
reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC0)];
printf(" Miscellaneous Information Register 0: 0x%08x\n", reg);
printf(" MSI Message number: 0x%02x\n",
- (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MSINUM));
- val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_GVASIZE);
+ PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MSINUM));
+ val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_GVASIZE);
printf(" Guest Virtual Address size: ");
if (val == PCI_SECURE_IOMMU_MISC0_GVASIZE_48B)
printf("48bits\n");
else
printf("0x%x(unknown)\n", val);
- val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_PASIZE);
+ val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_PASIZE);
printf(" Physical Address size: %dbits\n", val);
- val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_VASIZE);
+ val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_VASIZE);
printf(" Virtual Address size: %dbits\n", val);
onoff("ATS response address range reserved", reg,
PCI_SECURE_IOMMU_MISC0_ATSRESV);
printf(" Peripheral Page Request MSI Message number: 0x%02x\n",
- (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MISNPPR));
+ PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MISNPPR));
if (!havemisc1)
return;
@@ -1611,7 +1613,7 @@
reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)];
printf(" Miscellaneous Information Register 1: 0x%08x\n", reg);
printf(" MSI Message number (GA): 0x%02x\n",
- (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC1_MSINUM));
+ PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC1_MSINUM));
}
static void
@@ -1812,7 +1814,7 @@
}
onoff("Slot implemented", reg, PCIE_XCAP_SI);
printf(" Interrupt Message Number: 0x%02x\n",
- (unsigned int)__SHIFTOUT(reg, PCIE_XCAP_IRQ));
+ PCIREG_SHIFTOUT(reg, PCIE_XCAP_IRQ));
/* Device Capability Register */
reg = regs[o2i(capoff + PCIE_DCAP)];
@@ -1820,7 +1822,7 @@
printf(" Max Payload Size Supported: %u bytes max\n",
128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD));
printf(" Phantom Functions Supported: ");
- switch (__SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) {
+ switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) {
case 0x0:
printf("not available\n");
break;
@@ -1837,9 +1839,9 @@
printf(" Extended Tag Field Supported: %dbit\n",
(reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8);
printf(" Endpoint L0 Acceptable Latency: ");
- pci_print_pcie_L0s_latency(__SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY));
+ pci_print_pcie_L0s_latency(PCIREG_SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY));
printf(" Endpoint L1 Acceptable Latency: ");
- pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY));
+ pci_print_pcie_L1_latency(PCIREG_SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY));
onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON);
onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND);
onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND);
@@ -1847,8 +1849,8 @@
if (check_upstreamport) {
printf(" Captured Slot Power Limit: ");
pci_conf_print_pcie_power(
- __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL),
- __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE));
+ PCIREG_SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL),
+ PCIREG_SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE));
}
onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR);
@@ -1862,13 +1864,13 @@
onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR);
onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD);
printf(" Max Payload Size: %d byte\n",
- 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD));
+ 128 << PCIREG_SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD));
onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD);
onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS);
onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM);
onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP);
printf(" Max Read Request Size: %d byte\n",
- 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ));
+ 128 << PCIREG_SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ));
if (pcie_devtype == PCIE_XCAP_TYPE_PCIE2PCI)
onoff("Bridge Config Retry Enable", reg,
PCIE_DCSR_BRDG_CFG_RETRY);
@@ -1891,9 +1893,9 @@
printf(" Maximum Link Speed: ");
pci_print_pcie_linkspeed(PCIE_LCAP, reg & PCIE_LCAP_MAX_SPEED);
printf(" Maximum Link Width: x%u lanes\n",
- (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH));
+ PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH));
printf(" Active State PM Support: ");
- switch (__SHIFTOUT(reg, PCIE_LCAP_ASPM)) {
+ switch (PCIREG_SHIFTOUT(reg, PCIE_LCAP_ASPM)) {
case 0x0:
printf("No ASPM support\n");
break;
@@ -1908,11 +1910,11 @@
break;
}
printf(" L0 Exit Latency: ");
- pci_print_pcie_L0s_latency(__SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT));
+ pci_print_pcie_L0s_latency(PCIREG_SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT));
printf(" L1 Exit Latency: ");
- pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_LCAP_L1_EXIT));
+ pci_print_pcie_L1_latency(PCIREG_SHIFTOUT(reg, PCIE_LCAP_L1_EXIT));
printf(" Port Number: %u\n",
- (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_PORT));
+ PCIREG_SHIFTOUT(reg, PCIE_LCAP_PORT));
onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM);
onoff("Surprise Down Error Report", reg,
PCIE_LCAP_SURPRISE_DOWN);
@@ -1953,7 +1955,7 @@
onoff("Link Autonomous Bandwidth Interrupt Enable", reg,
PCIE_LCSR_LABIE);
printf(" DRS Signaling Control: ");
- switch (__SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) {
+ switch (PCIREG_SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) {
case 0:
printf("not reported\n");
break;
@@ -1973,9 +1975,9 @@
printf(" Link Status Register: 0x%04x\n", reg >> 16);
printf(" Negotiated Link Speed: ");
pci_print_pcie_linkspeed(PCIE_LCSR,
- __SHIFTOUT(reg, PCIE_LCSR_LINKSPEED));
+ PCIREG_SHIFTOUT(reg, PCIE_LCSR_LINKSPEED));
printf(" Negotiated Link Width: x%u lanes\n",
- (unsigned int)__SHIFTOUT(reg, PCIE_LCSR_NLW));
+ PCIREG_SHIFTOUT(reg, PCIE_LCSR_NLW));
onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR);
onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN);
onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG);
@@ -2000,8 +2002,8 @@
onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS);
onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC);
printf(" Slot Power Limit Value: ");
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