[src/trunk]: src/sys/uvm/pmap Make a comment less MIPS specific

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/7b3446590f22
branches:  trunk
changeset: 930589:7b3446590f22
user:      skrll <skrll%NetBSD.org@localhost>
date:      Thu Apr 09 08:55:45 2020 +0000

description:
Make a comment less MIPS specific

diffstat:

 sys/uvm/pmap/pmap_tlb.c |  19 ++++++++++---------
 1 files changed, 10 insertions(+), 9 deletions(-)

diffs (40 lines):

diff -r 0439ff4ad8f8 -r 7b3446590f22 sys/uvm/pmap/pmap_tlb.c
--- a/sys/uvm/pmap/pmap_tlb.c   Thu Apr 09 06:55:51 2020 +0000
+++ b/sys/uvm/pmap/pmap_tlb.c   Thu Apr 09 08:55:45 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap_tlb.c,v 1.30 2019/12/18 11:27:56 skrll Exp $      */
+/*     $NetBSD: pmap_tlb.c,v 1.31 2020/04/09 08:55:45 skrll Exp $      */
 
 /*-
  * Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(0, "$NetBSD: pmap_tlb.c,v 1.30 2019/12/18 11:27:56 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap_tlb.c,v 1.31 2020/04/09 08:55:45 skrll Exp $");
 
 /*
  * Manages address spaces in a TLB.
@@ -69,13 +69,14 @@
  *
  * Each pmap has two bitmaps: pm_active and pm_onproc.  Each bit in pm_active
  * indicates whether that pmap has an allocated ASID for a CPU.  Each bit in
- * pm_onproc indicates that pmap's ASID is active (equal to the ASID in COP 0
- * register EntryHi) on a CPU.  The bit number comes from the CPU's cpu_index().
- * Even though these bitmaps contain the bits for all CPUs, the bits that
- * correspond to the bits belonging to the CPUs sharing a TLB can only be
- * manipulated while holding that TLB's lock.  Atomic ops must be used to
- * update them since multiple CPUs may be changing different sets of bits at
- * same time but these sets never overlap.
+ * pm_onproc indicates that the pmap's ASID is in use, i.e. a CPU has it in its
+ * "current ASID" field, e.g. the ASID field of the COP 0 register EntryHi for
+ * MIPS, or the ASID field of TTBR0 for AA64.  The bit number used in these
+ * bitmaps comes from the CPU's cpu_index().  Even though these bitmaps contain
+ * the bits for all CPUs, the bits that  correspond to the bits belonging to
+ * the CPUs sharing a TLB can only be manipulated while holding that TLB's
+ * lock.  Atomic ops must be used to update them since multiple CPUs may be
+ * changing different sets of bits at same time but these sets never overlap.
  *
  * When a change to the local TLB may require a change in the TLB's of other
  * CPUs, we try to avoid sending an IPI if at all possible.  For instance, if