[src/trunk]: src/sys/arch/arm/arm Enable DCache Streaming Switch and Write Al...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/332729c890e9
branches:  trunk
changeset: 783539:332729c890e9
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Fri Dec 28 03:48:00 2012 +0000

description:
Enable DCache Streaming Switch and Write Allocate for Sheeva CPU.
This change improve system performance significantly.

diffstat:

 sys/arch/arm/arm/cpufunc.c |  14 ++++++++++++--
 1 files changed, 12 insertions(+), 2 deletions(-)

diffs (42 lines):

diff -r 4438227ea5bd -r 332729c890e9 sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c        Thu Dec 27 21:34:09 2012 +0000
+++ b/sys/arch/arm/arm/cpufunc.c        Fri Dec 28 03:48:00 2012 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc.c,v 1.118 2012/11/12 18:00:34 skrll Exp $      */
+/*     $NetBSD: cpufunc.c,v 1.119 2012/12/28 03:48:00 msaitoh Exp $    */
 
 /*
  * arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.118 2012/11/12 18:00:34 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.119 2012/12/28 03:48:00 msaitoh Exp $");
 
 #include "opt_compat_netbsd.h"
 #include "opt_cpuoptions.h"
@@ -3352,6 +3352,7 @@
 sheeva_setup(char *args)
 {
        int cpuctrl, cpuctrlmask;
+       uint32_t sheeva_ext;
 
        cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
            | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
@@ -3369,6 +3370,15 @@
 
        cpuctrl = parse_cpu_options(args, sheeva_options, cpuctrl);
 
+       /* Enable DCache Streaming Switch and Write Allocate */
+       __asm volatile("mrc p15, 1, %0, c15, c1, 0"
+           : "=r" (sheeva_ext));
+
+       sheeva_ext |= FC_DCACHE_STREAM_EN | FC_WR_ALLOC_EN;
+
+       __asm volatile("mcr p15, 1, %0, c15, c1, 0"
+           :: "r" (sheeva_ext));
+
        /*
         * Sheeva has L2 Cache.  Enable/Disable it here.
         * Really not support yet...