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[src/netbsd-7]: src/sys/dev/pci Pull up following revision(s) (requested by m...
details: https://anonhg.NetBSD.org/src/rev/0ba32a3ac164
branches: netbsd-7
changeset: 798694:0ba32a3ac164
user: martin <martin%NetBSD.org@localhost>
date: Fri Dec 12 19:03:17 2014 +0000
description:
Pull up following revision(s) (requested by msaitoh in ticket #312):
sys/dev/pci/pci_subr.c: revision 1.130
sys/dev/pci/pci_subr.c: revision 1.131
sys/dev/pci/pci_subr.c: revision 1.132
sys/dev/pci/pcireg.h: revision 1.97
sys/dev/pci/pcireg.h: revision 1.98
sys/dev/pci/pcireg.h: revision 1.99
sys/dev/pci/pci_subr.c: revision 1.127
sys/dev/pci/pci_subr.c: revision 1.128
sys/dev/pci/pci_subr.c: revision 1.129
Always print the Slot implemented bit in the PCIe Capabilities
Register using with onoff().
- Add some PCI subclass and interfaces.
- The interface of PCI_SUBCLASS_BRIDGE_RACEWAY is not decoded yet.
- Fix typo in a message.
- Add comment.
- Modify comment.
s/genric/generic/
Add comment.
Fix typo in comment.
Fix a bug that the specification revision of the Power Management function
was incorrectly printed in the output of capability "list".
The value is also printed in the detail output and it has no bug.
- Cleanup pci_conf_print_caplist. Use table. The reason why it loops twice
is that some capabilities appear multiple times (e.g. HyperTransport cap).
- Print the specification revision of Power Management and AGP not in
the capability list part but in the detail part.
Add some HyperTransport related defines. It's required for the MSI.
diffstat:
sys/dev/pci/pci_subr.c | 242 +++++++++++++++++++++++-------------------------
sys/dev/pci/pcireg.h | 55 +++++++++-
2 files changed, 166 insertions(+), 131 deletions(-)
diffs (truncated from 545 to 300 lines):
diff -r ba8cdf9083be -r 0ba32a3ac164 sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c Fri Dec 12 18:56:16 2014 +0000
+++ b/sys/dev/pci/pci_subr.c Fri Dec 12 19:03:17 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.124 2014/06/09 11:08:05 msaitoh Exp $ */
+/* $NetBSD: pci_subr.c,v 1.124.2.1 2014/12/12 19:03:17 martin Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.124 2014/06/09 11:08:05 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.124.2.1 2014/12/12 19:03:17 martin Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -88,7 +88,7 @@
/*
* Class 0x01.
- * Mass strage controller
+ * Mass storage controller
*/
/* ATA programming interface */
@@ -100,7 +100,16 @@
/* SATA programming interface */
static const struct pci_class pci_interface_sata[] = {
+ { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, },
{ "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, },
+ { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, },
+ { NULL, 0, NULL, },
+};
+
+/* Flash programming interface */
+static const struct pci_class pci_interface_nvm[] = {
+ { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, },
+ { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, },
{ NULL, 0, NULL, },
};
@@ -116,7 +125,8 @@
{ "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA,
pci_interface_sata, },
{ "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, },
- { "NVM", PCI_SUBCLASS_MASS_STORAGE_NVM, NULL, },
+ { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM,
+ pci_interface_nvm, },
{ "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -165,7 +175,7 @@
{ "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, },
{ "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, },
{ "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,},
- { "HD audio", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, },
+ { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, },
{ "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -193,13 +203,20 @@
{ NULL, 0, NULL, },
};
-/* Semi-transparent PCI-toPCI bridge programming interface */
+/* Semi-transparent PCI-to-PCI bridge programming interface */
static const struct pci_class pci_interface_stpci[] = {
{ "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, },
{ "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, },
{ NULL, 0, NULL, },
};
+/* Advanced Switching programming interface */
+static const struct pci_class pci_interface_advsw[] = {
+ { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, },
+ { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, },
+ { NULL, 0, NULL, },
+};
+
/* Subclasses */
static const struct pci_class pci_subclass_bridge[] = {
{ "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, },
@@ -215,6 +232,8 @@
{ "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI,
pci_interface_stpci, },
{ "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, },
+ { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW,
+ pci_interface_advsw, },
{ "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -226,7 +245,7 @@
/* Serial controller programming interface */
static const struct pci_class pci_interface_serial[] = {
- { "genric XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, },
+ { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, },
{ "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, },
{ "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, },
{ "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, },
@@ -241,8 +260,8 @@
{ "", PCI_INTERFACE_PARALLEL, NULL,},
{ "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,},
{ "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,},
- { "IEEE1284", PCI_INTERFACE_PARALLEL_IEEE1284, NULL,},
- { "IEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,},
+ { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,},
+ { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,},
{ NULL, 0, NULL,},
};
@@ -278,7 +297,7 @@
/* PIC programming interface */
static const struct pci_class pci_interface_pic[] = {
- { "genric 8259", PCI_INTERFACE_PIC_8259, NULL, },
+ { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, },
{ "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, },
{ "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, },
{ "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, },
@@ -288,7 +307,7 @@
/* DMA programming interface */
static const struct pci_class pci_interface_dma[] = {
- { "genric 8237", PCI_INTERFACE_DMA_8237, NULL, },
+ { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, },
{ "ISA", PCI_INTERFACE_DMA_ISA, NULL, },
{ "EISA", PCI_INTERFACE_DMA_EISA, NULL, },
{ NULL, 0, NULL, },
@@ -296,9 +315,10 @@
/* Timer programming interface */
static const struct pci_class pci_interface_tmr[] = {
- { "genric 8254", PCI_INTERFACE_TIMER_8254, NULL, },
+ { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, },
{ "ISA", PCI_INTERFACE_TIMER_ISA, NULL, },
{ "EISA", PCI_INTERFACE_TIMER_EISA, NULL, },
+ { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, },
{ NULL, 0, NULL, },
};
@@ -369,6 +389,7 @@
{ "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, },
{ "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, },
{ "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, },
+ { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -429,7 +450,7 @@
*/
static const struct pci_class pci_subclass_wireless[] = {
{ "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, },
- { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, },
+ { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, },
{ "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, },
{ "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, },
{ "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, },
@@ -487,7 +508,7 @@
*/
static const struct pci_class pci_subclass_dasp[] = {
{ "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, },
- { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, },
+ { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, },
{ "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, },
{ "management", PCI_SUBCLASS_DASP_MGMT, NULL, },
{ "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, },
@@ -1011,6 +1032,20 @@
printf("\n");
}
+static void
+pci_conf_print_agp_cap(const pcireg_t *regs, int capoff)
+{
+ pcireg_t rval;
+
+ printf("\n AGP Capabilities Register\n");
+
+ rval = regs[o2i(capoff)];
+ printf(" Revision: %d.%d\n",
+ PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval));
+
+ /* XXX need more */
+}
+
static const char *
pci_conf_print_pcipm_cap_aux(uint16_t caps)
{
@@ -1401,8 +1436,7 @@
printf("unknown\n");
break;
}
- if (check_slot && (reg & PCIE_XCAP_SI) != 0)
- printf(" Slot implemented\n");
+ onoff("Slot implemented", reg, PCIE_XCAP_SI);
printf(" Interrupt Message Number: %x\n",
(unsigned int)((reg & PCIE_XCAP_IRQ) >> 27));
@@ -1839,6 +1873,35 @@
onoff("Transaction Pending", reg, PCI_AFSR_TP);
}
+static struct {
+ pcireg_t cap;
+ const char *name;
+ void (*printfunc)(const pcireg_t *, int);
+} pci_captab[] = {
+ { PCI_CAP_RESERVED0, "reserved", NULL },
+ { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap },
+ { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap },
+ { PCI_CAP_VPD, "VPD", NULL },
+ { PCI_CAP_SLOTID, "SlotID", NULL },
+ { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap },
+ { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL },
+ { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap },
+ { PCI_CAP_LDT, "HyperTransport", NULL },
+ { PCI_CAP_VENDSPEC, "Vendor-specific",
+ pci_conf_print_vendspec_cap },
+ { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap },
+ { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL },
+ { PCI_CAP_HOTPLUG, "Hot-Plug", NULL },
+ { PCI_CAP_SUBVENDOR, "Subsystem vendor ID",
+ pci_conf_print_subsystem_cap },
+ { PCI_CAP_AGP8, "AGP 8x", NULL },
+ { PCI_CAP_SECURE, "Secure Device", NULL },
+ { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap },
+ { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap },
+ { PCI_CAP_SATA, "SATA", NULL },
+ { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap }
+};
+
static void
pci_conf_print_caplist(
#ifdef _KERNEL
@@ -1847,11 +1910,16 @@
const pcireg_t *regs, int capoff)
{
int off;
+ pcireg_t foundcap;
pcireg_t rval;
- int pcie_off = -1, pcipm_off = -1, msi_off = -1, pcix_off = -1;
- int vendspec_off = -1, msix_off = -1;
- int debugport_off = -1, subsystem_off = -1, pciaf_off = -1;
+ bool foundtable[__arraycount(pci_captab)];
+ unsigned int i;
+ /* Clear table */
+ for (i = 0; i < __arraycount(pci_captab); i++)
+ foundtable[i] = false;
+
+ /* Print capability register's offset and the type first */
for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
off != 0;
off = PCI_CAPLIST_NEXT(regs[o2i(off)])) {
@@ -1859,113 +1927,39 @@
printf(" Capability register at 0x%02x\n", off);
printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval));
- switch (PCI_CAPLIST_CAP(rval)) {
- case PCI_CAP_RESERVED0:
- printf("reserved");
- break;
- case PCI_CAP_PWRMGMT:
- printf("Power Management, rev. %s",
- pci_conf_print_pcipm_cap_pmrev(
- (rval >> 0) & 0x07));
- pcipm_off = off;
- break;
- case PCI_CAP_AGP:
- printf("AGP, rev. %d.%d",
- PCI_CAP_AGP_MAJOR(rval),
- PCI_CAP_AGP_MINOR(rval));
- break;
- case PCI_CAP_VPD:
- printf("VPD");
- break;
- case PCI_CAP_SLOTID:
- printf("SlotID");
- break;
- case PCI_CAP_MSI:
- printf("MSI");
- msi_off = off;
- break;
- case PCI_CAP_CPCI_HOTSWAP:
- printf("CompactPCI Hot-swapping");
- break;
- case PCI_CAP_PCIX:
- pcix_off = off;
- printf("PCI-X");
- break;
- case PCI_CAP_LDT:
- printf("LDT");
- break;
- case PCI_CAP_VENDSPEC:
- vendspec_off = off;
- printf("Vendor-specific");
- break;
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