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[src/trunk]: src/sys/arch/aarch64/include More whitespace
details: https://anonhg.NetBSD.org/src/rev/ae923f6cce4c
branches: trunk
changeset: 834270:ae923f6cce4c
user: skrll <skrll%NetBSD.org@localhost>
date: Sun Aug 05 07:49:02 2018 +0000
description:
More whitespace
diffstat:
sys/arch/aarch64/include/armreg.h | 580 +++++++++++++++++++-------------------
1 files changed, 290 insertions(+), 290 deletions(-)
diffs (truncated from 774 to 300 lines):
diff -r d3706b92e89f -r ae923f6cce4c sys/arch/aarch64/include/armreg.h
--- a/sys/arch/aarch64/include/armreg.h Sun Aug 05 06:48:50 2018 +0000
+++ b/sys/arch/aarch64/include/armreg.h Sun Aug 05 07:49:02 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.13 2018/08/01 13:42:58 skrll Exp $ */
+/* $NetBSD: armreg.h,v 1.14 2018/08/05 07:49:02 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -80,12 +80,12 @@
#define CTR_EL0_L1IP_PIPT 3 // Physical Index, Physical Tag
#define CTR_EL0_IMIN_LINE __BITS(3,0) // Icache MIN LINE size (log2 - 2)
-AARCH64REG_READ_INLINE(dczid_el0) // Data Cache Zero ID Register
+AARCH64REG_READ_INLINE(dczid_el0) // Data Cache Zero ID Register
#define DCZID_DZP __BIT(4) // Data Zero Prohibited
#define DCZID_BS __BITS(3,0) // Block Size (log2 - 2)
-AARCH64REG_READ_INLINE(fpcr) // Floating Point Control Register
+AARCH64REG_READ_INLINE(fpcr) // Floating Point Control Register
AARCH64REG_WRITE_INLINE(fpcr)
#define FPCR_AHP __BIT(26) // Alternative Half Precision
@@ -144,7 +144,7 @@
*/
AARCH64REG_READ_INLINE(aidr_el1)
-AARCH64REG_READ_INLINE2(cbar_el1, s3_1_c15_c3_0) // Cortex-A57
+AARCH64REG_READ_INLINE2(cbar_el1, s3_1_c15_c3_0) // Cortex-A57
#define CBAR_PA __BITS(47,18)
@@ -261,75 +261,75 @@
AARCH64REG_READ_INLINE(mvfr0_el1)
-#define MVFR0_FPROUND __BITS(31,28)
-#define MVFR0_FPROUND_NEAREST 0
+#define MVFR0_FPROUND __BITS(31,28)
+#define MVFR0_FPROUND_NEAREST 0
#define MVFR0_FPROUND_ALL 1
-#define MVFR0_FPSHVEC __BITS(27,24)
+#define MVFR0_FPSHVEC __BITS(27,24)
#define MVFR0_FPSHVEC_NONE 0
-#define MVFR0_FPSHVEC_SHVEC 1
-#define MVFR0_FPSQRT __BITS(23,20)
+#define MVFR0_FPSHVEC_SHVEC 1
+#define MVFR0_FPSQRT __BITS(23,20)
#define MVFR0_FPSQRT_NONE 0
#define MVFR0_FPSQRT_VSQRT 1
-#define MVFR0_FPDIVIDE __BITS(19,16)
-#define MVFR0_FPDIVIDE_NONE 0
-#define MVFR0_FPDIVIDE_VDIV 1
-#define MVFR0_FPTRAP __BITS(15,12)
+#define MVFR0_FPDIVIDE __BITS(19,16)
+#define MVFR0_FPDIVIDE_NONE 0
+#define MVFR0_FPDIVIDE_VDIV 1
+#define MVFR0_FPTRAP __BITS(15,12)
#define MVFR0_FPTRAP_NONE 0
#define MVFR0_FPTRAP_TRAP 1
-#define MVFR0_FPDP __BITS(11,8)
+#define MVFR0_FPDP __BITS(11,8)
#define MVFR0_FPDP_NONE 0
#define MVFR0_FPDP_VFPV2 1
#define MVFR0_FPDP_VFPV3 2
-#define MVFR0_FPSP __BITS(7,4)
+#define MVFR0_FPSP __BITS(7,4)
#define MVFR0_FPSP_NONE 0
#define MVFR0_FPSP_VFPV2 1
#define MVFR0_FPSP_VFPV3 2
-#define MVFR0_SIMDREG __BITS(3,0)
+#define MVFR0_SIMDREG __BITS(3,0)
#define MVFR0_SIMDREG_NONE 0
-#define MVFR0_SIMDREG_16x64 1
-#define MVFR0_SIMDREG_32x64 2
+#define MVFR0_SIMDREG_16x64 1
+#define MVFR0_SIMDREG_32x64 2
AARCH64REG_READ_INLINE(mvfr1_el1)
-#define MVFR1_SIMDFMAC __BITS(31,28)
-#define MVFR1_SIMDFMAC_NONE 0
-#define MVFR1_SIMDFMAC_FMAC 1
-#define MVFR1_FPHP __BITS(27,24)
+#define MVFR1_SIMDFMAC __BITS(31,28)
+#define MVFR1_SIMDFMAC_NONE 0
+#define MVFR1_SIMDFMAC_FMAC 1
+#define MVFR1_FPHP __BITS(27,24)
#define MVFR1_FPHP_NONE 0
-#define MVFR1_FPHP_HALF_SINGLE 1
-#define MVFR1_FPHP_HALF_DOUBLE 2
-#define MVFR1_SIMDHP __BITS(23,20)
+#define MVFR1_FPHP_HALF_SINGLE 1
+#define MVFR1_FPHP_HALF_DOUBLE 2
+#define MVFR1_SIMDHP __BITS(23,20)
#define MVFR1_SIMDHP_NONE 0
#define MVFR1_SIMDHP_HALF 1
-#define MVFR1_SIMDSP __BITS(19,16)
+#define MVFR1_SIMDSP __BITS(19,16)
#define MVFR1_SIMDSP_NONE 0
-#define MVFR1_SIMDSP_SINGLE 1
-#define MVFR1_SIMDINT __BITS(15,12)
+#define MVFR1_SIMDSP_SINGLE 1
+#define MVFR1_SIMDINT __BITS(15,12)
#define MVFR1_SIMDINT_NONE 0
-#define MVFR1_SIMDINT_INTEGER 1
-#define MVFR1_SIMDLS __BITS(11,8)
+#define MVFR1_SIMDINT_INTEGER 1
+#define MVFR1_SIMDLS __BITS(11,8)
#define MVFR1_SIMDLS_NONE 0
-#define MVFR1_SIMDLS_LOADSTORE 1
-#define MVFR1_FPDNAN __BITS(7,4)
+#define MVFR1_SIMDLS_LOADSTORE 1
+#define MVFR1_FPDNAN __BITS(7,4)
#define MVFR1_FPDNAN_NONE 0
#define MVFR1_FPDNAN_NAN 1
-#define MVFR1_FPFTZ __BITS(3,0)
+#define MVFR1_FPFTZ __BITS(3,0)
#define MVFR1_FPFTZ_NONE 0
-#define MVFR1_FPFTZ_DENORMAL 1
+#define MVFR1_FPFTZ_DENORMAL 1
AARCH64REG_READ_INLINE(mvfr2_el1)
-#define MVFR2_FPMISC __BITS(7,4)
+#define MVFR2_FPMISC __BITS(7,4)
#define MVFR2_FPMISC_NONE 0
#define MVFR2_FPMISC_SEL 1
-#define MVFR2_FPMISC_DROUND 2
-#define MVFR2_FPMISC_ROUNDINT 3
-#define MVFR2_FPMISC_MAXMIN 4
-#define MVFR2_SIMDMISC __BITS(3,0)
-#define MVFR2_SIMDMISC_NONE 0
-#define MVFR2_SIMDMISC_DROUND 1
+#define MVFR2_FPMISC_DROUND 2
+#define MVFR2_FPMISC_ROUNDINT 3
+#define MVFR2_FPMISC_MAXMIN 4
+#define MVFR2_SIMDMISC __BITS(3,0)
+#define MVFR2_SIMDMISC_NONE 0
+#define MVFR2_SIMDMISC_DROUND 1
#define MVFR2_SIMDMISC_ROUNDINT 2
-#define MVFR2_SIMDMISC_MAXMIN 3
+#define MVFR2_SIMDMISC_MAXMIN 3
AARCH64REG_READ_INLINE(revidr_el1)
@@ -339,29 +339,29 @@
AARCH64REG_READ_INLINE(cpacr_el1) // Coprocessor Access Control Regiser
AARCH64REG_WRITE_INLINE(cpacr_el1)
-#define CPACR_TTA __BIT(28) // System Register Access Traps
-#define CPACR_FPEN __BITS(21,20)
-#define CPACR_FPEN_NONE __SHIFTIN(0, CPACR_FPEN)
-#define CPACR_FPEN_EL1 __SHIFTIN(1, CPACR_FPEN)
-#define CPACR_FPEN_NONE_2 __SHIFTIN(2, CPACR_FPEN)
-#define CPACR_FPEN_ALL __SHIFTIN(3, CPACR_FPEN)
+#define CPACR_TTA __BIT(28) // System Register Access Traps
+#define CPACR_FPEN __BITS(21,20)
+#define CPACR_FPEN_NONE __SHIFTIN(0, CPACR_FPEN)
+#define CPACR_FPEN_EL1 __SHIFTIN(1, CPACR_FPEN)
+#define CPACR_FPEN_NONE_2 __SHIFTIN(2, CPACR_FPEN)
+#define CPACR_FPEN_ALL __SHIFTIN(3, CPACR_FPEN)
AARCH64REG_READ_INLINE(csselr_el1) // Cache Size Selection Register
AARCH64REG_WRITE_INLINE(csselr_el1)
-#define CSSELR_LEVEL __BITS(3,1) // Cache level of required cache
-#define CSSELR_IND __BIT(0) // Instruction not Data bit
+#define CSSELR_LEVEL __BITS(3,1) // Cache level of required cache
+#define CSSELR_IND __BIT(0) // Instruction not Data bit
AARCH64REG_READ_INLINE(daif) // Debug Async Irq Fiq mask register
AARCH64REG_WRITE_INLINE(daif)
AARCH64REG_WRITEIMM_INLINE(daifclr)
AARCH64REG_WRITEIMM_INLINE(daifset)
-#define DAIF_D __BIT(9) // Debug Exception Mask
-#define DAIF_A __BIT(8) // SError Abort Mask
-#define DAIF_I __BIT(7) // IRQ Mask
-#define DAIF_F __BIT(6) // FIQ Mask
-#define DAIF_SETCLR_SHIFT 6 // for daifset/daifclr #imm shift
+#define DAIF_D __BIT(9) // Debug Exception Mask
+#define DAIF_A __BIT(8) // SError Abort Mask
+#define DAIF_I __BIT(7) // IRQ Mask
+#define DAIF_F __BIT(6) // FIQ Mask
+#define DAIF_SETCLR_SHIFT 6 // for daifset/daifclr #imm shift
AARCH64REG_READ_INLINE(elr_el1) // Exception Link Register
AARCH64REG_WRITE_INLINE(elr_el1)
@@ -369,44 +369,44 @@
AARCH64REG_READ_INLINE(esr_el1) // Exception Symdrone Register
AARCH64REG_WRITE_INLINE(esr_el1)
-#define ESR_EC __BITS(31,26) // Exception Cause
-#define ESR_EC_UNKNOWN 0x00 // AXX: Unknown Reason
-#define ESR_EC_WFX 0x01 // AXX: WFI or WFE instruction execution
-#define ESR_EC_CP15_RT 0x03 // A32: MCR/MRC access to CP15 !EC=0
-#define ESR_EC_CP15_RRT 0x04 // A32: MCRR/MRRC access to CP15 !EC=0
-#define ESR_EC_CP14_RT 0x05 // A32: MCR/MRC access to CP14
-#define ESR_EC_CP14_DT 0x06 // A32: LDC/STC access to CP14
-#define ESR_EC_FP_ACCESS 0x07 // AXX: Access to SIMD/FP Registers
-#define ESR_EC_FPID 0x08 // A32: MCR/MRC access to CP10 !EC=7
-#define ESR_EC_CP14_RRT 0x0c // A32: MRRC access to CP14
-#define ESR_EC_ILL_STATE 0x0e // AXX: Illegal Execution State
-#define ESR_EC_SVC_A32 0x11 // A32: SVC Instruction Execution
-#define ESR_EC_HVC_A32 0x12 // A32: HVC Instruction Execution
-#define ESR_EC_SMC_A32 0x13 // A32: SMC Instruction Execution
-#define ESR_EC_SVC_A64 0x15 // A64: SVC Instruction Execution
-#define ESR_EC_HVC_A64 0x16 // A64: HVC Instruction Execution
-#define ESR_EC_SMC_A64 0x17 // A64: SMC Instruction Execution
-#define ESR_EC_SYS_REG 0x18 // A64: MSR/MRS/SYS instruction (!EC0/1/7)
-#define ESR_EC_INSN_ABT_EL0 0x20 // AXX: Instruction Abort (EL0)
-#define ESR_EC_INSN_ABT_EL1 0x21 // AXX: Instruction Abort (EL1)
-#define ESR_EC_PC_ALIGNMENT 0x22 // AXX: Misaligned PC
-#define ESR_EC_DATA_ABT_EL0 0x24 // AXX: Data Abort (EL0)
-#define ESR_EC_DATA_ABT_EL1 0x25 // AXX: Data Abort (EL1)
-#define ESR_EC_SP_ALIGNMENT 0x26 // AXX: Misaligned SP
-#define ESR_EC_FP_TRAP_A32 0x28 // A32: FP Exception
-#define ESR_EC_FP_TRAP_A64 0x2c // A64: FP Exception
-#define ESR_EC_SERROR 0x2f // AXX: SError Interrupt
-#define ESR_EC_BRKPNT_EL0 0x30 // AXX: Breakpoint Exception (EL0)
-#define ESR_EC_BRKPNT_EL1 0x31 // AXX: Breakpoint Exception (EL1)
-#define ESR_EC_SW_STEP_EL0 0x32 // AXX: Software Step (EL0)
-#define ESR_EC_SW_STEP_EL1 0x33 // AXX: Software Step (EL1)
-#define ESR_EC_WTCHPNT_EL0 0x34 // AXX: Watchpoint (EL0)
-#define ESR_EC_WTCHPNT_EL1 0x35 // AXX: Watchpoint (EL1)
-#define ESR_EC_BKPT_INSN_A32 0x38 // A32: BKPT Instruction Execution
-#define ESR_EC_VECTOR_CATCH 0x3a // A32: Vector Catch Exception
-#define ESR_EC_BKPT_INSN_A64 0x3c // A64: BKPT Instruction Execution
-#define ESR_IL __BIT(25) // Instruction Length (1=32-bit)
-#define ESR_ISS __BITS(24,0) // Instruction Specific Syndrome
+#define ESR_EC __BITS(31,26) // Exception Cause
+#define ESR_EC_UNKNOWN 0x00 // AXX: Unknown Reason
+#define ESR_EC_WFX 0x01 // AXX: WFI or WFE instruction execution
+#define ESR_EC_CP15_RT 0x03 // A32: MCR/MRC access to CP15 !EC=0
+#define ESR_EC_CP15_RRT 0x04 // A32: MCRR/MRRC access to CP15 !EC=0
+#define ESR_EC_CP14_RT 0x05 // A32: MCR/MRC access to CP14
+#define ESR_EC_CP14_DT 0x06 // A32: LDC/STC access to CP14
+#define ESR_EC_FP_ACCESS 0x07 // AXX: Access to SIMD/FP Registers
+#define ESR_EC_FPID 0x08 // A32: MCR/MRC access to CP10 !EC=7
+#define ESR_EC_CP14_RRT 0x0c // A32: MRRC access to CP14
+#define ESR_EC_ILL_STATE 0x0e // AXX: Illegal Execution State
+#define ESR_EC_SVC_A32 0x11 // A32: SVC Instruction Execution
+#define ESR_EC_HVC_A32 0x12 // A32: HVC Instruction Execution
+#define ESR_EC_SMC_A32 0x13 // A32: SMC Instruction Execution
+#define ESR_EC_SVC_A64 0x15 // A64: SVC Instruction Execution
+#define ESR_EC_HVC_A64 0x16 // A64: HVC Instruction Execution
+#define ESR_EC_SMC_A64 0x17 // A64: SMC Instruction Execution
+#define ESR_EC_SYS_REG 0x18 // A64: MSR/MRS/SYS instruction (!EC0/1/7)
+#define ESR_EC_INSN_ABT_EL0 0x20 // AXX: Instruction Abort (EL0)
+#define ESR_EC_INSN_ABT_EL1 0x21 // AXX: Instruction Abort (EL1)
+#define ESR_EC_PC_ALIGNMENT 0x22 // AXX: Misaligned PC
+#define ESR_EC_DATA_ABT_EL0 0x24 // AXX: Data Abort (EL0)
+#define ESR_EC_DATA_ABT_EL1 0x25 // AXX: Data Abort (EL1)
+#define ESR_EC_SP_ALIGNMENT 0x26 // AXX: Misaligned SP
+#define ESR_EC_FP_TRAP_A32 0x28 // A32: FP Exception
+#define ESR_EC_FP_TRAP_A64 0x2c // A64: FP Exception
+#define ESR_EC_SERROR 0x2f // AXX: SError Interrupt
+#define ESR_EC_BRKPNT_EL0 0x30 // AXX: Breakpoint Exception (EL0)
+#define ESR_EC_BRKPNT_EL1 0x31 // AXX: Breakpoint Exception (EL1)
+#define ESR_EC_SW_STEP_EL0 0x32 // AXX: Software Step (EL0)
+#define ESR_EC_SW_STEP_EL1 0x33 // AXX: Software Step (EL1)
+#define ESR_EC_WTCHPNT_EL0 0x34 // AXX: Watchpoint (EL0)
+#define ESR_EC_WTCHPNT_EL1 0x35 // AXX: Watchpoint (EL1)
+#define ESR_EC_BKPT_INSN_A32 0x38 // A32: BKPT Instruction Execution
+#define ESR_EC_VECTOR_CATCH 0x3a // A32: Vector Catch Exception
+#define ESR_EC_BKPT_INSN_A64 0x3c // A64: BKPT Instruction Execution
+#define ESR_IL __BIT(25) // Instruction Length (1=32-bit)
+#define ESR_ISS __BITS(24,0) // Instruction Specific Syndrome
#define ESR_ISS_CV __BIT(24) // common
#define ESR_ISS_COND __BITS(23,20) // common
#define ESR_ISS_WFX_TRAP_INSN __BIT(0) // for ESR_EC_WFX
@@ -438,38 +438,38 @@
#define ESR_ISS_DATAABORT_WnR __BIT(6) // for ESC_RC_DATA_ABT_EL[01]
#define ESR_ISS_DATAABORT_DFSC __BITS(0,5) // for ESC_RC_DATA_ABT_EL[01]
-#define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_0 0x00
-#define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_1 0x01
-#define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_2 0x02
-#define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_3 0x03
-#define ESR_ISS_FSC_TRANSLATION_FAULT_0 0x04
-#define ESR_ISS_FSC_TRANSLATION_FAULT_1 0x05
-#define ESR_ISS_FSC_TRANSLATION_FAULT_2 0x06
-#define ESR_ISS_FSC_TRANSLATION_FAULT_3 0x07
-#define ESR_ISS_FSC_ACCESS_FAULT_0 0x08
-#define ESR_ISS_FSC_ACCESS_FAULT_1 0x09
-#define ESR_ISS_FSC_ACCESS_FAULT_2 0x0a
-#define ESR_ISS_FSC_ACCESS_FAULT_3 0x0b
-#define ESR_ISS_FSC_PERM_FAULT_0 0x0c
-#define ESR_ISS_FSC_PERM_FAULT_1 0x0d
-#define ESR_ISS_FSC_PERM_FAULT_2 0x0e
-#define ESR_ISS_FSC_PERM_FAULT_3 0x0f
-#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT 0x10
-#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_0 0x14
-#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_1 0x15
-#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_2 0x16
-#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_3 0x17
-#define ESR_ISS_FSC_SYNC_PARITY_ERROR 0x18
-#define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_0 0x1c
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