[src/netbsd-9]: src/sys/arch/x86/x86 Pull up following revision(s) (requested...

[martin <martin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/43c94278f092
branches:  netbsd-9
changeset: 843674:43c94278f092
user:      martin <martin%NetBSD.org@localhost>
date:      Sat Dec 14 12:24:23 2019 +0000

description:
Pull up following revision(s) (requested by maxv in ticket #550):

        sys/arch/x86/x86/spectre.c: revision 1.32

Check CPUID.IBRS in addition to ARCH_CAP.IBRS_ALL. For clarity, and also
because VirtualBox clears the former but forgets to clear the latter (which
makes us hit a #GP on RDMSR).

diffstat:

 sys/arch/x86/x86/spectre.c |  22 +++++++++++-----------
 1 files changed, 11 insertions(+), 11 deletions(-)

diffs (48 lines):

diff -r de617af36eca -r 43c94278f092 sys/arch/x86/x86/spectre.c
--- a/sys/arch/x86/x86/spectre.c        Sat Dec 14 12:22:43 2019 +0000
+++ b/sys/arch/x86/x86/spectre.c        Sat Dec 14 12:24:23 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: spectre.c,v 1.29.2.2 2019/11/12 18:24:37 martin Exp $  */
+/*     $NetBSD: spectre.c,v 1.29.2.3 2019/12/14 12:24:23 martin Exp $  */
 
 /*
  * Copyright (c) 2018-2019 NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: spectre.c,v 1.29.2.2 2019/11/12 18:24:37 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: spectre.c,v 1.29.2.3 2019/12/14 12:24:23 martin Exp $");
 
 #include "opt_spectre.h"
 
@@ -126,20 +126,20 @@
                if (cpuid_level >= 7) {
                        x86_cpuid(7, descs);
 
-                       if (descs[3] & CPUID_SEF_ARCH_CAP) {
-                               msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
-                               if (msr & IA32_ARCH_IBRS_ALL) {
-                                       v2_mitigation_method =
-                                           V2_MITIGATION_INTEL_ENHANCED_IBRS;
-                                       return;
+                       if (descs[3] & CPUID_SEF_IBRS) {
+                               if (descs[3] & CPUID_SEF_ARCH_CAP) {
+                                       msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
+                                       if (msr & IA32_ARCH_IBRS_ALL) {
+                                               v2_mitigation_method =
+                                                   V2_MITIGATION_INTEL_ENHANCED_IBRS;
+                                               return;
+                                       }
                                }
-                       }
 #ifdef __x86_64__
-                       if (descs[3] & CPUID_SEF_IBRS) {
                                v2_mitigation_method = V2_MITIGATION_INTEL_IBRS;
                                return;
+#endif
                        }
-#endif
                }
                v2_mitigation_method = V2_MITIGATION_NONE;
        } else if (cpu_vendor == CPUVENDOR_AMD) {