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[src/trunk]: src/sys/arch/evbarm/beagle OMAP5/OMAP4 MP Changes + better OMAP5...
details: https://anonhg.NetBSD.org/src/rev/acae370feb9e
branches: trunk
changeset: 794950:acae370feb9e
user: matt <matt%NetBSD.org@localhost>
date: Sat Mar 29 14:47:30 2014 +0000
description:
OMAP5/OMAP4 MP Changes + better OMAP5 support.
diffstat:
sys/arch/evbarm/beagle/beagle_machdep.c | 62 +++++++++++++++++-----
sys/arch/evbarm/beagle/beagle_start.S | 90 +++++++++++++++++++++++++++-----
2 files changed, 122 insertions(+), 30 deletions(-)
diffs (truncated from 328 to 300 lines):
diff -r d994020edc68 -r acae370feb9e sys/arch/evbarm/beagle/beagle_machdep.c
--- a/sys/arch/evbarm/beagle/beagle_machdep.c Sat Mar 29 14:30:16 2014 +0000
+++ b/sys/arch/evbarm/beagle/beagle_machdep.c Sat Mar 29 14:47:30 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: beagle_machdep.c,v 1.55 2013/08/29 15:46:17 riz Exp $ */
+/* $NetBSD: beagle_machdep.c,v 1.56 2014/03/29 14:47:30 matt Exp $ */
/*
* Machine dependent functions for kernel setup for TI OSK5912 board.
@@ -125,7 +125,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: beagle_machdep.c,v 1.55 2013/08/29 15:46:17 riz Exp $");
+__KERNEL_RCSID(0, "$NetBSD: beagle_machdep.c,v 1.56 2014/03/29 14:47:30 matt Exp $");
#include "opt_machdep.h"
#include "opt_ddb.h"
@@ -140,6 +140,7 @@
#include "prcm.h"
#include "sdhc.h"
#include "ukbd.h"
+#include "arml2cc.h"
#include <sys/param.h>
#include <sys/systm.h>
@@ -196,9 +197,16 @@
#ifdef CPU_CORTEXA9
#include <arm/cortex/pl310_reg.h>
+#include <arm/cortex/scu_reg.h>
+
+#include <arm/cortex/a9tmr_var.h>
#include <arm/cortex/pl310_var.h>
#endif
+#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15)
+#include <arm/cortex/gtmr_var.h>
+#endif
+
#include <evbarm/include/autoconf.h>
#include <evbarm/beagle/beagle.h>
@@ -481,14 +489,29 @@
/* The console is going to try to map things. Give pmap a devmap. */
pmap_devmap_register(devmap);
consinit();
+#ifdef CPU_CORTEXA15
+#ifdef MULTIPROCESSOR
+ arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);
+#endif
+#endif
#if defined(OMAP_4XXX)
+#if NARML2CC > 0
/*
* Probe the PL310 L2CC
*/
- const bus_space_handle_t pl310_bh = OMAP4_L2CC_BASE +
- OMAP_L4_PERIPHERAL_VBASE - OMAP_L4_PERIPHERAL_BASE;
+ const bus_space_handle_t pl310_bh = OMAP4_L2CC_BASE
+ + OMAP_L4_PERIPHERAL_VBASE - OMAP_L4_PERIPHERAL_BASE;
arml2cc_init(&omap_bs_tag, pl310_bh, 0);
+ beagle_putchar('l');
#endif
+#ifdef MULTIPROCESSOR
+ const bus_space_handle_t scu_bh = OMAP4_SCU_BASE
+ + OMAP_L4_PERIPHERAL_VBASE - OMAP_L4_PERIPHERAL_BASE;
+ uint32_t scu_cfg = bus_space_read_4(&omap_bs_tag, scu_bh, SCU_CFG);
+ arm_cpu_max = 1 + (scu_cfg & SCU_CFG_CPUMAX);
+ beagle_putchar('s');
+#endif
+#endif /* OMAP_4XXX */
#if defined(TI_AM335X) && defined(VERBOSE_INIT_ARM)
am335x_cpu_clk(); // find our CPU speed.
#endif
@@ -498,6 +521,7 @@
printf("\nuboot arg = %#x, %#x, %#x, %#x\n",
uboot_args[0], uboot_args[1], uboot_args[2], uboot_args[3]);
+
#ifdef KGDB
kgdb_port_init();
#endif
@@ -518,7 +542,7 @@
printf("initarm: Configuring system ...\n");
#endif
-#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA9) || defined(CPU_CORTEXA15)
+#if !defined(CPU_CORTEXA8)
printf("initarm: cbar=%#x\n", armreg_cbar_read());
#endif
@@ -533,6 +557,15 @@
ram_size = emif_memprobe();
#endif
+#ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS
+ if (ram_size > KERNEL_VM_BASE - KERNEL_BASE) {
+ printf("%s: dropping RAM size from %luMB to %uMB\n",
+ __func__, (unsigned long) (ram_size >> 20),
+ (KERNEL_VM_BASE - KERNEL_BASE) >> 20);
+ ram_size = KERNEL_VM_BASE - KERNEL_BASE;
+ }
+#endif
+
/*
* If MEMSIZE specified less than what we really have, limit ourselves
* to that.
@@ -998,24 +1031,23 @@
#endif
#if defined(OMAP_4430)
prop_dictionary_set_uint16(dict, "nports", 2);
-#if 0
- prop_dictionary_set_bool(dict, "phy-reset", true);
-#else
prop_dictionary_set_bool(dict, "phy-reset", false);
-#endif
prop_dictionary_set_cstring(dict, "port0-mode", "none");
prop_dictionary_set_int16(dict, "port0-gpio", -1);
-#if 0
prop_dictionary_set_cstring(dict, "port1-mode", "phy");
-#else
- prop_dictionary_set_cstring(dict, "port1-mode", "none");
-#endif
prop_dictionary_set_int16(dict, "port1-gpio", 62);
prop_dictionary_set_bool(dict, "port1-gpioval", true);
-#if 0
omap2_gpio_ctl(1, GPIO_PIN_OUTPUT);
- omap2_gpio_write(1, 1); // Enable Hub
+ omap2_gpio_write(1, 1); // Power Hub
#endif
+#if defined(OMAP_5430)
+ prop_dictionary_set_uint16(dict, "nports", 3);
+ prop_dictionary_set_cstring(dict, "port0-mode", "none");
+ prop_dictionary_set_int16(dict, "port0-gpio", -1);
+ prop_dictionary_set_cstring(dict, "port1-mode", "hsic");
+ prop_dictionary_set_int16(dict, "port1-gpio", -1);
+ prop_dictionary_set_cstring(dict, "port2-mode", "hsic");
+ prop_dictionary_set_int16(dict, "port2-gpio", -1);
#endif
return;
}
diff -r d994020edc68 -r acae370feb9e sys/arch/evbarm/beagle/beagle_start.S
--- a/sys/arch/evbarm/beagle/beagle_start.S Sat Mar 29 14:30:16 2014 +0000
+++ b/sys/arch/evbarm/beagle/beagle_start.S Sat Mar 29 14:47:30 2014 +0000
@@ -99,7 +99,7 @@
#include <arm/cortex/a9tmr_reg.h>
#endif
-RCSID("$NetBSD: beagle_start.S,v 1.18 2013/08/18 06:34:02 matt Exp $")
+RCSID("$NetBSD: beagle_start.S,v 1.19 2014/03/29 14:47:30 matt Exp $")
#if defined(VERBOSE_INIT_ARM)
#define XPUTC(n) mov r0, n; bl xputc
@@ -111,6 +111,12 @@
#define INIT_MEMSIZE 128
#define TEMP_L1_TABLE (0x80000000 + INIT_MEMSIZE * 0x100000 - L1_TABLE_SIZE)
+#if defined(CPU_CORTEXA9)
+#define MD_CPU_HATCH _C_LABEL(a9tmr_init_cpu_clock)
+#endif
+#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15)
+#define MD_CPU_HATCH _C_LABEL(gtmr_init_cpu_clock)
+#endif
/*
* Kernel start routine for BEAGLEBOARD boards.
@@ -131,13 +137,11 @@
movt r4, #:upper16:uboot_args
stmia r4, {r0-r3}
-#ifdef CPU_CORTEXA9
/*
- * Turn on the SCU if we are on a Cortex-A9
+ * bring the CPU into a known state (turn on SMP, caches, etc).
*/
- bl a9_start
+ bl cortex_init
XPUTC(#67)
-#endif
/*
* Set up a preliminary mapping in the MMU to allow us to run
@@ -157,6 +161,18 @@
movt r0, #:upper16:TEMP_L1_TABLE
bl arm_cpuinit
XPUTC(#90)
+
+#ifdef MULTIPROCESSOR
+ // Now spin up the second processors into the same state we are now.
+ XPUTC(#77)
+ XPUTC(#80)
+ XPUTC(#60)
+ // Make sure the contents of the data cache are in memory
+ // for the secondary CPUs
+ bl _C_LABEL(armv7_dcache_wbinv_all)
+ bl omap_mpinit
+ XPUTC(#62)
+#endif
XPUTC(#13)
XPUTC(#10)
@@ -173,71 +189,115 @@
#include <arm/cortex/a9_mpsubr.S>
+#ifdef MULTIPROCESSOR
+omap_mpinit:
+ mrc p15, 0, r0, c0, c0, 5 // MPIDR read
+ ubfx r1, r0, #30, #2 // get top 2 bits
+ cmp r1, #2 // =2?
+ bxne lr // no, not MP
+
+ movw r3, #:lower16:OMAP4_WUGEN_BASE
+ movt r3, #:upper16:OMAP4_WUGEN_BASE
+
+ // First we setup the address for the secondaries to jump to.
+ adr r0, cortex_mpstart
+ str r0, [r3, #OMAP4_AUX_CORE_BOOT1]
+ dsb
+
+ // tell the secondary boot rom(s) to exit their loop
+ ldr r1, [r3, #OMAP4_AUX_CORE_BOOT0] // load AUX_CORE_BOOT_0
+ orr r1, r1, #0xf0 // add mask for cpu #1
+ str r1, [r3, #OMAP4_AUX_CORE_BOOT0] // store AUX_CORE_BOOT_0
+ dsb
+
+ // Now we kick it and return.
+ sev
+ movw r3, #:lower16:arm_cpu_hatched
+ movt r3, #:upper16:arm_cpu_hatched
+
+ // Let's wait for the secondary to hatch.
+ mov r1, #0x1000000
+1: dmb
+ ldr r0, [r3]
+ cmp r0, #0
+ bxne lr
+ subs r1, r1, #1
+ bne 1b
+
+ XPUTC(#84)
+
+ bx lr
+END(omap_mpinit)
+#endif
+
.Lmmu_init_table:
/* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable, shareable */
MMU_INIT(KERNEL_BASE, KERNEL_BASE,
(INIT_MEMSIZE * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
- L1_S_PROTO | L1_S_APv7_KRW | L1_S_B | L1_S_C | L1_S_V6_S)
+#ifdef MULTIPROCESSOR
+ L1_S_V6_S |
+#endif
+ L1_S_PROTO | L1_S_APv7_KRW | L1_S_B | L1_S_C)
/* Map first 1MB of L4 CORE (so console will work) */
MMU_INIT(OMAP_L4_CORE_VBASE, OMAP_L4_CORE_BASE,
(OMAP_L4_CORE_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
- L1_S_PROTO | L1_S_APv7_KRW)
+ L1_S_PROTO | L1_S_APv7_KRW | L1_S_V6_XN)
#if OMAP_L4_CORE_BASE <= CONSADDR \
&& CONSADDR < OMAP_L4_CORE_BASE + OMAP_L4_CORE_SIZE
/* Map first 1MB of L4 CORE 1:1 (so console will work) */
MMU_INIT(OMAP_L4_CORE_BASE, OMAP_L4_CORE_BASE,
(OMAP_L4_CORE_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
- L1_S_PROTO | L1_S_APv7_KRW)
+ L1_S_PROTO | L1_S_APv7_KRW | L1_S_V6_XN)
#endif
/* Map first 4MB of L4 PERIPHERAL (so console will work) */
MMU_INIT(OMAP_L4_PERIPHERAL_VBASE, OMAP_L4_PERIPHERAL_BASE,
(OMAP_L4_PERIPHERAL_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
- L1_S_PROTO | L1_S_APv7_KRW)
+ L1_S_PROTO | L1_S_APv7_KRW | L1_S_V6_XN)
#if OMAP_L4_PERIPHERAL_BASE <= CONSADDR \
&& CONSADDR < OMAP_L4_PERIPHERAL_BASE + OMAP_L4_PERIPHERAL_SIZE
/* Map first 1MB of L4 PERIPHERAL 1:1 (so console will work) */
MMU_INIT(OMAP_L4_PERIPHERAL_BASE, OMAP_L4_PERIPHERAL_BASE,
(OMAP_L4_PERIPHERAL_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
- L1_S_PROTO | L1_S_APv7_KRW)
+ L1_S_PROTO | L1_S_APv7_KRW | L1_S_V6_XN)
#endif
#if defined(OMAP_L4_WAKEUP_BASE) && defined(OMAP_L4_WAKEUP_VBASE)
/* Map all 4MB of L4 WAKEUP (so console will work) */
MMU_INIT(OMAP_L4_WAKEUP_VBASE, OMAP_L4_WAKEUP_BASE,
(OMAP_L4_WAKEUP_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
- L1_S_PROTO | L1_S_APv7_KRW)
+ L1_S_PROTO | L1_S_APv7_KRW | L1_S_V6_XN)
#endif
#ifdef OMAP_L4_FAST_BASE
/* Map first 1MB of L4 FAST (so console will work) */
MMU_INIT(OMAP_L4_FAST_VBASE, OMAP_L4_FAST_BASE,
(OMAP_L4_FAST_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
- L1_S_PROTO | L1_S_APv7_KRW)
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