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[src/netbsd-7]: src/sys/arch Pull up the following revisions, requested by sk...
details: https://anonhg.NetBSD.org/src/rev/1e8129928461
branches: netbsd-7
changeset: 798777:1e8129928461
user: martin <martin%NetBSD.org@localhost>
date: Sun Jan 04 11:19:00 2015 +0000
description:
Pull up the following revisions, requested by skrll in #373:
sys/arch/arm/samsung/exynos4_loc.c 1.10-1.11
sys/arch/arm/samsung/exynos4_reg.h 1.8-1.13
sys/arch/arm/samsung/exynos5_loc.c 1.8-1.12
sys/arch/arm/samsung/exynos5_reg.h 1.11-1.20
sys/arch/arm/samsung/exynos_gpio.c 1.7-1.12
sys/arch/arm/samsung/exynos_i2c.c 1.2-1.3
sys/arch/arm/samsung/exynos_intr.h 1.2
sys/arch/arm/samsung/exynos_io.c 1.7-1.8
sys/arch/arm/samsung/exynos_io.h 1.5-1.6
sys/arch/arm/samsung/exynos_reg.h 1.8-1.13
sys/arch/arm/samsung/exynos_smc.S 1.2-1.3
sys/arch/arm/samsung/exynos_soc.c 1.15-1.27
sys/arch/arm/samsung/exynos_usb.c 1.8-1.13
sys/arch/arm/samsung/exynos_var.h 1.13-1.18
sys/arch/arm/samsung/exynos_wdt.c 1.5
sys/arch/arm/samsung/mct.c 1.4-1.5
sys/arch/arm/samsung/mct_reg.h 1.2
sys/arch/arm/samsung/mct_var.h 1.3
sys/arch/arm/samsung/smc.h 1.2
sys/arch/arm/samsung/sscom.c 1.7
sys/arch/evbarm/odroid/odroid_machdep.c 1.25-1.39
sys/arch/evbarm/odroid/odroid_start.S 1.4-1.6
sys/arch/evbarm/conf/std.odroid 1.3-1.5
sys/arch/evbarm/conf/ODROID delete
sys/arch/evbarm/conf/ODROID-U 1.10-1.17
sys/arch/evbarm/conf/ODROID_INSTALL delete
sys/arch/evbarm/conf/ODROID-XU 1.1-1.4
Improve ODROID support.
diffstat:
sys/arch/arm/samsung/exynos4_loc.c | 8 +-
sys/arch/arm/samsung/exynos4_reg.h | 46 +-
sys/arch/arm/samsung/exynos5_loc.c | 17 +-
sys/arch/arm/samsung/exynos5_reg.h | 93 +++-
sys/arch/arm/samsung/exynos_gpio.c | 124 +++++-
sys/arch/arm/samsung/exynos_i2c.c | 16 +-
sys/arch/arm/samsung/exynos_intr.h | 2 +
sys/arch/arm/samsung/exynos_io.c | 8 +-
sys/arch/arm/samsung/exynos_io.h | 4 +-
sys/arch/arm/samsung/exynos_reg.h | 55 +-
sys/arch/arm/samsung/exynos_smc.S | 7 +-
sys/arch/arm/samsung/exynos_soc.c | 720 ++++++++++++++++++++++++++++++-
sys/arch/arm/samsung/exynos_usb.c | 198 +-------
sys/arch/arm/samsung/exynos_var.h | 24 +-
sys/arch/arm/samsung/exynos_wdt.c | 27 +-
sys/arch/arm/samsung/mct.c | 9 +-
sys/arch/arm/samsung/mct_reg.h | 3 +-
sys/arch/arm/samsung/mct_var.h | 3 +-
sys/arch/arm/samsung/smc.h | 3 +-
sys/arch/arm/samsung/sscom.c | 16 +-
sys/arch/evbarm/conf/ODROID | 262 -----------
sys/arch/evbarm/conf/ODROID-U | 62 +-
sys/arch/evbarm/conf/ODROID-XU | 249 +++++++++++
sys/arch/evbarm/conf/ODROID_INSTALL | 11 -
sys/arch/evbarm/conf/std.odroid | 6 +-
sys/arch/evbarm/odroid/odroid_machdep.c | 300 ++++++++-----
sys/arch/evbarm/odroid/odroid_start.S | 58 ++-
27 files changed, 1620 insertions(+), 711 deletions(-)
diffs (truncated from 3318 to 300 lines):
diff -r 75623ce26e56 -r 1e8129928461 sys/arch/arm/samsung/exynos4_loc.c
--- a/sys/arch/arm/samsung/exynos4_loc.c Sat Jan 03 05:53:44 2015 +0000
+++ b/sys/arch/arm/samsung/exynos4_loc.c Sun Jan 04 11:19:00 2015 +0000
@@ -1,3 +1,5 @@
+/* $NetBSD: exynos4_loc.c,v 1.9.4.1 2015/01/04 11:19:00 martin Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -139,6 +141,10 @@
#define IRQ_EINT_1 IRQ_SPI(17)
#define IRQ_EINT_0 IRQ_SPI(16)
+/* rest of PPI's marked reserved */
+#define IRQ_MCT_L IRQ_PPI(12)
+#define IRQ_MCT_G IRQ_PPI(10)
+
#define IRQ_CPU_NIRQOUT_3 EXYNOS_COMBINERIRQ(19, 6)
#define IRQ_PARITYFAILSCU_3 EXYNOS_COMBINERIRQ(19, 5)
#define IRQ_PARITYFAIL3 EXYNOS_COMBINERIRQ(19, 4)
@@ -266,7 +272,7 @@
static const struct exyo_locators exynos4_locators[] = {
{ "exyogpio", 0, 0, NOPORT, NOINTR, 0 },
{ "exyoiic", 0, 0, NOPORT, NOINTR, 0 },
- { "mct", OFFANDSIZE(,MCT), NOPORT, IRQ_G0_IRQ, 0 },
+ { "mct", OFFANDSIZE(,MCT), NOPORT, IRQ_MCT_G, 0 },
{ "exyowdt", OFFANDSIZE(,WDT), NOPORT, IRQ_WDT, 0 },
{ "sscom", OFFANDSIZE(,UART0), 0, IRQ_UART0, 0 },
{ "sscom", OFFANDSIZE(,UART1), 1, IRQ_UART1, 0 },
diff -r 75623ce26e56 -r 1e8129928461 sys/arch/arm/samsung/exynos4_reg.h
--- a/sys/arch/arm/samsung/exynos4_reg.h Sat Jan 03 05:53:44 2015 +0000
+++ b/sys/arch/arm/samsung/exynos4_reg.h Sun Jan 04 11:19:00 2015 +0000
@@ -1,4 +1,5 @@
-/* $NetBSD */
+/* $NetBSD: exynos4_reg.h,v 1.7.4.1 2015/01/04 11:19:00 martin Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -115,8 +116,12 @@
#define EXYNOS4_SYSREG_OFFSET 0x00010000
#define EXYNOS4_PMU_OFFSET 0x00020000 /* Power Management Unit */
-#define EXYNOS4_CMU_TOP_PART_OFFSET 0x00030000 /* XXX unknown XXX */
-#define EXYNOS4_CMU_CORE_ISP_PART_OFFSET 0x00040000 /* XXX unknown XXX */
+#define EXYNOS4_CMU_TOP_PART_OFFSET 0x00030000 /* Clock(s) management unit */
+#define EXYNOS4_CMU_EPLL 0x0003C010 /* Audio and ext. interf. clock */
+#define EXYNOS4_CMU_VPLL 0x0003C020 /* Video core (dither?) clock */
+#define EXYNOS4_CMU_CORE_ISP_PART_OFFSET 0x00040000 /* Clock(s) management unit */
+#define EXYNOS4_CMU_MPLL 0x00040008 /* MEM cntr. clock */
+#define EXYNOS4_CMU_APLL 0x00044000 /* ARM core clock */
#define EXYNOS4_MCT_OFFSET 0x00050000 /* Multi Core Timer */
#define EXYNOS4_WDT_OFFSET 0x00060000 /* Watch Dog Timer */
#define EXYNOS4_RTC_OFFSET 0x00070000 /* Real Time Clock */
@@ -207,8 +212,9 @@
#define EXYNOS4_SROMC_OFFSET 0x02570000
#define EXYNOS4_USB2HOST_OFFSET 0x02580000
-#define EXYNOS4_USBHOST0_OFFSET 0x02580000 /* USB EHCI */
-#define EXYNOS4_USBHOST1_OFFSET 0x02590000 /* USB OHCI companion to EHCI (paired) */
+#define EXYNOS4_USB2_HOST_EHCI_OFFSET 0x02580000
+#define EXYNOS4_USB2_HOST_OHCI_OFFSET 0x02590000
+#define EXYNOS4_USB2_HOST_PHYCTRL_OFFSET 0x025B0000
#define EXYNOS4_USBOTG1_OFFSET 0x025B0000 /* USB On The Go interface */
#define EXYNOS4_PDMA0_OFFSET 0x02680000 /* Peripheral DMA */
@@ -262,13 +268,33 @@
#define EXYNOS4_PWMTIMER_OFFSET 0x039D0000
/* AUDIOCORE */
-#define EXYNOS4_AUDIOCORE_OFFSET 0x04060000 /* on 1Mb L1 chunk */
+#define EXYNOS4_AUDIOCORE_OFFSET 0x04000000 /* on 1Mb L1 chunk */
#define EXYNOS4_AUDIOCORE_VBASE (EXYNOS_CORE_VBASE + EXYNOS4_AUDIOCORE_OFFSET)
-#define EXYNOS4_AUDIOCORE_PBASE 0x03860000 /* Audio SFR */
-#define EXYNOS4_AUDIOCORE_SIZE 0x00001000
+#define EXYNOS4_AUDIOCORE_PBASE 0x03800000 /* Audio SFR */
+#define EXYNOS4_AUDIOCORE_SIZE 0x00100000
+
+#define EXYNOS4_GPIO_I2S0_OFFSET (EXYNOS4_AUDIOCORE_OFFSET + 0x00060000)
-#define EXYNOS4_GPIO_I2S0_OFFSET (EXYNOS4_AUDIOCORE_OFFSET + 0x00000000)
+/* used Exynos4 USB PHY registers */
+#define USB_PHYPWR 0x00
+#define PHYPWR_FORCE_SUSPEND __BIT(1)
+#define PHYPWR_ANALOG_POWERDOWN __BIT(3)
+#define PHYPWR_OTG_DISABLE __BIT(4)
+#define PHYPWR_SLEEP_PHY0 __BIT(5)
+#define PHYPWR_NORMAL_MASK 0x19
+#define PHYPWR_NORMAL_MASK_PHY0 (__BITS(3,3) | 1)
+#define PHYPWR_NORMAL_MASK_PHY1 __BITS(6,3)
+#define PHYPWR_NORMAL_MASK_HSIC0 __BITS(9,3)
+#define PHYPWR_NORMAL_MASK_HSIC1 __BITS(12,3)
+#define USB_PHYCLK 0x04 /* holds FSEL_CLKSEL_ */
+#define USB_RSTCON 0x08
+#define RSTCON_SWRST __BIT(0)
+#define RSTCON_HLINK_RWRST __BIT(1)
+#define RSTCON_DEVPHYLINK_SWRST __BIT(2)
+#define RSTCON_DEVPHY_SWRST __BITS(0,3)
+#define RSTCON_HOSTPHY_SWRST __BITS(3,4)
+#define RSTCON_HOSTPHYLINK_SWRST __BITS(7,4)
-#endif /* _ARM_SAMSUNG_EXYNOS5_REG_H_ */
+#endif /* _ARM_SAMSUNG_EXYNOS4_REG_H_ */
diff -r 75623ce26e56 -r 1e8129928461 sys/arch/arm/samsung/exynos5_loc.c
--- a/sys/arch/arm/samsung/exynos5_loc.c Sat Jan 03 05:53:44 2015 +0000
+++ b/sys/arch/arm/samsung/exynos5_loc.c Sun Jan 04 11:19:00 2015 +0000
@@ -1,3 +1,5 @@
+/* $NetBSD: exynos5_loc.c,v 1.7.4.1 2015/01/04 11:19:00 martin Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -91,7 +93,7 @@
#define IRQ_CPU_NFIQ_1 IRQ_SPI(67)
#define IRQ_CPU_NFIQ_0 IRQ_SPI(66)
#define IRQ_TMU IRQ_SPI(65)
-#define IRQ_I2C IRQ_SPI(64)
+#define IRQ_HDMI_I2C IRQ_SPI(64)
#define IRQ_I2C7 IRQ_SPI(63)
#define IRQ_I2C6 IRQ_SPI(62)
#define IRQ_I2C5 IRQ_SPI(61)
@@ -213,11 +215,14 @@
EXYNOS5##p##_##n##_OFFSET, 0x10000
static const struct exyo_locators exynos5_locators[] = {
+ { "exyogpio", 0, 0, NOPORT, NOINTR, 0 },
+ { "exyoiic", 0, 0, NOPORT, NOINTR, 0 },
{ "exyowdt", OFFANDSIZE(,WDT), NOPORT, IRQ_WDT, 0 },
{ "sscom", OFFANDSIZE(,UART0), 0, IRQ_UART0, 0 },
{ "sscom", OFFANDSIZE(,UART1), 1, IRQ_UART1, 0 },
{ "sscom", OFFANDSIZE(,UART2), 2, IRQ_UART2, 0 },
{ "sscom", OFFANDSIZE(,UART3), 3, IRQ_UART3, 0 },
+ { "exyousb", OFFANDSIZE(,USB2HOST), NOPORT, IRQ_USB_HOST20, 0 },
};
const struct exyo_locinfo exynos5_locinfo = {
@@ -228,6 +233,16 @@
/* flag signal the use of gpio */
static const struct exyo_locators exynos5_i2c_locators[] = {
+ /* busname, sdabit, slcbit, func */
+ { "iic0", OFFANDSIZE(,I2C0), 0, IRQ_I2C0_USI0, 1 , "GPB3", 0, 1, 2 },
+ { "iic1", OFFANDSIZE(,I2C1), 1, IRQ_I2C1_USI1, 1 , "GPB3", 2, 3, 2 },
+ { "iic2", OFFANDSIZE(,I2C2), 2, IRQ_I2C2_USI2, 1 , "GPA0", 6, 7, 3 },
+ { "iic3", OFFANDSIZE(,I2C3), 3, IRQ_I2C3_USI3, 1 , "GPA1", 2, 3, 3 },
+ { "iic4", OFFANDSIZE(,I2C4), 4, IRQ_I2C4, 1 , "GPA2", 0, 1, 3 },
+ { "iic5", OFFANDSIZE(,I2C5), 5, IRQ_I2C5, 1 , "GPA2", 2, 3, 3 },
+ { "iic6", OFFANDSIZE(,I2C6), 6, IRQ_I2C6, 1 , "GPB1", 3, 4, 4 },
+ { "iic7", OFFANDSIZE(,I2C7), 7, IRQ_I2C7, 1 , "GPB2", 2, 3, 3 },
+ { "iic8", OFFANDSIZE(,I2CHDMI), 8, IRQ_HDMI_I2C, 0 , "", 0, 0, 0 },
};
diff -r 75623ce26e56 -r 1e8129928461 sys/arch/arm/samsung/exynos5_reg.h
--- a/sys/arch/arm/samsung/exynos5_reg.h Sat Jan 03 05:53:44 2015 +0000
+++ b/sys/arch/arm/samsung/exynos5_reg.h Sun Jan 04 11:19:00 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos5_reg.h,v 1.10 2014/06/11 14:49:50 reinoud Exp $ */
+/* $NetBSD: exynos5_reg.h,v 1.10.4.1 2015/01/04 11:19:00 martin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -55,10 +55,19 @@
#define EXYNOS5_CORE_SIZE 0x0f000000
#define EXYNOS5_SDRAM_PBASE 0x40000000
-#define EXYNOS5_CMU_COREPART_OFFSET 0x00010000
-#define EXYNOS5_CMU_TOPPART_OFFSET 0x00020000
-#define EXYNOS5_CMU_MEMPART_OFFSET 0x00030000
+#define EXYNOS5_CMU_CORE_PART_OFFSET 0x00010000
+#define EXYNOS5_CMU_APLL 0x00010000 /* ARM core clock */
+#define EXYNOS5_CMU_MPLL 0x00014000 /* MEM cntr. clock */
+#define EXYNOS5_CMU_TOP_PART_OFFSET 0x00020000
+#define EXYNOS5_CMU_CPLL 0x00020020 /* Video hardware codec clock */
+#define EXYNOS5_CMU_DPLL 0x00020030 /* Audio and ext. interf. clock */
+#define EXYNOS5_CMU_VPLL 0x00020040 /* Dither PLL (EMI reduction) clock */
+#define EXYNOS5_CMU_GPLL 0x00020050 /* Graphic 3D proc. clock */
+#define EXYNOS5_CMU_MEM_PART_OFFSET 0x00030000
+#define EXYNOS5_CMU_BPLL 0x00030010
+#define EXYNOS5_CMU_KPLL 0x00038000
#define EXYNOS5_ALIVE_OFFSET 0x00040000
+#define EXYNOS5_PMU_OFFSET 0x00040000 /* alias */
#define EXYNOS5_SYSREG_OFFSET 0x00050000
#define EXYNOS5_TMU_OFFSET 0x00060000
#define EXYNOS5_MONOTONIC_CNT_OFFSET 0x000C0000
@@ -94,7 +103,7 @@
#define EXYNOS5_AS_A_LEFT_BUS_OFFSET 0x00CE0000
#define EXYNOS5_AS_A_RIGHT0_BUS_OFFSET 0x00CF0000
#define EXYNOS5_AS_A_DISP1_BUS_OFFSET 0x00D00000
-#define EXYNOS5_C2C_GPIO_OFFSET 0x00D10000
+#define EXYNOS5_GPIO_C2C_OFFSET 0x00D10000
#define EXYNOS5_DREXII_OFFSET 0x00DD0000
#define EXYNOS5_AS_A_EFCON_OFFSET 0x00DE0000
#define EXYNOS5_AP_C2C_OFFSET 0x00E00000
@@ -128,7 +137,7 @@
#define EXYNOS5_USB2HOST_OFFSET 0x02110000
#define EXYNOS5_USB2_HOST_EHCI_OFFSET 0x02110000
#define EXYNOS5_USB2_HOST_OHCI_OFFSET 0x02120000
-#define EXYNOS5_USB2_HOST_CTRL_OFFSET 0x02130000
+#define EXYNOS5_USB2_HOST_PHYCTRL_OFFSET 0x02130000
#define EXYNOS5_USB2_DEVICE_LINK_OFFSET 0x02140000
#define EXYNOS5_MIPI_HSI_OFFSET 0x02160000
@@ -180,7 +189,7 @@
#define EXYNOS5_I2C5_OFFSET 0x02CB0000
#define EXYNOS5_I2C6_OFFSET 0x02CC0000
#define EXYNOS5_I2C7_OFFSET 0x02CD0000
-#define EXYNOS5_I2C_HDMI_OFFSET 0x02CE0000
+#define EXYNOS5_I2CHDMI_OFFSET 0x02CE0000
#define EXYNOS5_USI_OFFSET 0x02D00000
#define EXYNOS5_TSADC_OFFSET 0x02D10000
#define EXYNOS5_SPI0_OFFSET 0x02D20000
@@ -252,6 +261,7 @@
#define EXYNOS5_SYSMMU_GSCALER1_OFFSET 0x03E90000
#define EXYNOS5_SYSMMU_GSCALER2_OFFSET 0x03EA0000
#define EXYNOS5_SYSMMU_GSCALER3_OFFSET 0x03EB0000
+#define EXYNOS5_GPIO_USB_OFFSET 0x04000000
#define EXYNOS5_AS_A_GSCALER_OFFSET 0x04220000
#define EXYNOS5_DISP1_MIX_OFFSET 0x04400000
#define EXYNOS5_DISP1_ENH_OFFSET 0x04410000
@@ -347,6 +357,75 @@
/* AUDIOCORE */
#define EXYNOS5_AUDIOCORE_VBASE (EXYNOS_CORE_VBASE + EXYNOS5_CORE_SIZE)
#define EXYNOS5_AUDIOCORE_PBASE 0x03800000 /* Audio SFR */
+#define EXYNOS5_GPIO_I2S_OFFSET (EXYNOS5_CORE_SIZE + 0x00060000)
#define EXYNOS5_AUDIOCORE_SIZE 0x00070000
+
+/* used Exynos5 USB PHY registers */
+#define USB_PHY_HOST_CTRL0 0x00
+#define HOST_CTRL0_PHY_SWRST __BIT(0)
+#define HOST_CTRL0_LINK_SWRST __BIT(1)
+#define HOST_CTRL0_UTMI_SWRST __BIT(2)
+#define HOST_CTRL0_WORDINTERFACE __BIT(3)
+#define HOST_CTRL0_FORCESUSPEND __BIT(4)
+#define HOST_CTRL0_FORCESLEEP __BIT(5)
+#define HOST_CTRL0_SIDDQ __BIT(6)
+#define HOST_CTRL0_COMMONON_N __BIT(9) /* common block configuration during suspend */
+#define HOST_CTRL0_RETENABLE __BIT(10)
+#define HOST_CTRL0_TESTBURNIN __BIT(11)
+#define HOST_CTRL0_FSEL_MASK __BITS(16, 18) /* holds FSEL_CLKSEL_ */
+#define HOST_CTRL0_REFCLKSEL_MASK __BITS(19, 20)
+#define HOST_CTRL0_REFCLKSEL_XTAL 0
+#define HOST_CTRL0_REFCLKSEL_EXTL 1
+#define HOST_CTRL0_REFCLKSEL_CLKCORE 2
+#define HOST_CTRL0_PHY_SWRST_ALL __BIT(31)
+
+#define USB_PHY_HSIC_CTRL1 0x10
+#define USB_PHY_HSIC_TUNE1 0x14
+#define USB_PHY_HSIC_CTRL2 0x20
+#define USB_PHY_HSIC_TUNE2 0x24
+
+#define HSIC_CTRL_PHY_SWRST __BIT(0)
+#define HSIC_CTRL_UTMI_SWRST __BIT(2)
+#define HSIC_CTRL_WORDINTERFACE __BIT(3)
+#define HSIC_CTRL_FORCESUSPEND __BIT(4)
+#define HSIC_CTRL_FORCESLEEP __BIT(5)
+#define HSIC_CTRL_SIDDQ __BIT(6)
+#define HSIC_CTRL_REFCLKDIV_MASK __BITS(16,22)
+#define HSIC_CTRL_REFCLKDIV_12 0x24
+#define HSIC_CTRL_REFCLKDIV_15 0x1c
+#define HSIC_CTRL_REFCLKDIV_16 0x1a
+#define HSIC_CTRL_REFCLKDIV_19_2 0x15
+#define HSIC_CTRL_REFCLKDIV_20 0x14
+#define HSIC_CTRL_REFCLKSEL_MASK __BITS(23, 24)
+#define HSIC_CTRL_REFCLKSEL_DEFAULT 2
+
+#define USB_PHY_HOST_EHCICTRL 0x30
+#define HOST_EHCICTRL_ENA_INCR16 __BIT(26)
+#define HOST_EHCICTRL_ENA_INCR8 __BIT(27)
+#define HOST_EHCICTRL_ENA_INCR4 __BIT(28)
+#define HOST_EHCICTRL_ENA_INCRXALIGN __BIT(29)
+
+#define USB_PHY_HOST_OHCICTRL 0x34
+#define HOST_OHCICTRL_CLKCK_RST __BIT(0)
+#define HOST_OHCICTRL_CNTSEL __BIT(1)
+#define HOST_OHCICTRL_APPSTARTCLK __BIT(2)
+#define HOST_OHCICTRL_SUSPLGCY __BIT(3)
+
+#define USB_PHY_OTG_SYS 0x38
+#define OTG_SYS_FORCESUSPEND __BIT(0)
+#define OTG_SYS_SIDDQ_UOTG __BIT(1)
+#define OTG_SYS_OTGDISABLE __BIT(2)
+#define OTG_SYS_FORCESLEEP __BIT(3)
+#define OTG_SYS_FSEL_MASK __BITS(4, 6) /* holds FSEL_CLKSEL_ */
+#define OTG_SYS_COMMON_ON __BIT(7)
+#define OTG_SYS_IDPULLUP_UOTG __BIT(8)
+#define OTG_SYS_REFCLKSEL_MASK __BITS(9, 10)
+#define OTG_SYS_REFCLKSEL_XTAL __SHIFTIN(OTG_SYS_REFCLKSEL_MASK, 0)
+#define OTG_SYS_REFCLKSEL_EXTL __SHIFTIN(OTG_SYS_REFCLKSEL_MASK, 1)
+#define OTG_SYS_REFCLKSEL_CLKCORE __SHIFTIN(OTG_SYS_REFCLKSEL_MASK, 2)
+#define OTG_SYS_PHY0_SWRST __BIT(12)
+#define OTG_SYS_LINK_SWRST_UOTG __BIT(13)
+#define OTG_SYS_PHYLINK_SWRST __BIT(14)
+
#endif /* _ARM_SAMSUNG_EXYNOS5_REG_H_ */
diff -r 75623ce26e56 -r 1e8129928461 sys/arch/arm/samsung/exynos_gpio.c
--- a/sys/arch/arm/samsung/exynos_gpio.c Sat Jan 03 05:53:44 2015 +0000
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