[src/trunk]: src/sys/arch/mips/mips In working around loongson errata clear B...

[maya <maya%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/1857bf852d73
branches:  trunk
changeset: 825958:1857bf852d73
user:      maya <maya%NetBSD.org@localhost>
date:      Tue Aug 08 09:33:41 2017 +0000

description:
In working around loongson errata clear BTB and RAS, same as
other operating systems.

15 Errata: Issue of Out-of-order in loongson (translated)

In loongson 2F, because of the branch prediction, sometimes the CPU
may fetch the instructions from some unexpected area (for example I/O
space). It is an invalid operation. There are two ways for the CPU to
choose the branch target. The first one is predicting the branch
target according to the branch target history. The second one is
calculating the branch target by the ALU. There are most 8
instructions in the instruction window at the same time in loongson2f
(Remember the loongson 2f is superscalar, right?). Hence, the
branch target of an indirect branch(such as jr) could be got(may be
predicted by the branch target history) earlier and the instrctions of
the branch target could be prefetched even if there are branch
instructions before it. As a result, it is possible to fetch the
instructions from I/O region( say out-of the physical address range of
[0- 0x100000]) in kernel model because of the instruction prefetch of
the branch target.

There are some suggestions to prevent prefetching instructions from
the I/O region in kernel mode.

(1) When switching from user model to kernel model, you should flush
the branch target history such as BTB and RAS.
(2) Doing some tricks to the indirect branch target to make sure that
the indirect branch target can not be in the I/O region.

diffstat:

 sys/arch/mips/mips/mipsX_subr.S |  12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diffs (54 lines):

diff -r dfa2df2f7bed -r 1857bf852d73 sys/arch/mips/mips/mipsX_subr.S
--- a/sys/arch/mips/mips/mipsX_subr.S   Tue Aug 08 08:24:34 2017 +0000
+++ b/sys/arch/mips/mips/mipsX_subr.S   Tue Aug 08 09:33:41 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mipsX_subr.S,v 1.100 2017/05/15 10:59:24 skrll Exp $   */
+/*     $NetBSD: mipsX_subr.S,v 1.101 2017/08/08 09:33:41 maya Exp $    */
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -1289,7 +1289,7 @@
         * Save a minimum of registers to see if this is rdhwr $3,$29
         */
 #ifdef MIPS3_LOONGSON2
-       li      k0, MIPS_DIAG_BTB_CLEAR
+       li      k0,  MIPS_DIAG_BTB_CLEAR | MIPS_DIAG_RAS_DISABLE 
        mtc0    k0, MIPS_COP_0_DIAG
 #endif
        /* K1 already has CURLWP */
@@ -1354,7 +1354,7 @@
         * Save all the registers except the kernel temporaries onto the stack.
         */
 #ifdef MIPS3_LOONGSON2
-       li      k0, MIPS_DIAG_BTB_CLEAR
+       li      k0, MIPS_DIAG_BTB_CLEAR | MIPS_DIAG_RAS_DISABLE
        mtc0    k0, MIPS_COP_0_DIAG
 #endif
        /* K1 already has CURLWP */
@@ -1469,7 +1469,7 @@
  * We don't need to save s0 - s8 because the compiler does it for us.
  */
 #ifdef MIPS3_LOONGSON2
-       li      k0, MIPS_DIAG_BTB_CLEAR
+       li      k0, MIPS_DIAG_BTB_CLEAR | MIPS_DIAG_RAS_DISABLE
        mtc0    k0, MIPS_COP_0_DIAG
 #endif
        /* k1 contains curlwp */
@@ -1661,7 +1661,7 @@
         * Save all the registers but kernel temporaries onto the stack.
         */
 #ifdef MIPS3_LOONGSON2
-       li      k0, MIPS_DIAG_BTB_CLEAR
+       li      k0, MIPS_DIAG_BTB_CLEAR | MIPS_DIAG_RAS_DISABLE
        mtc0    k0, MIPS_COP_0_DIAG
 #endif
        /* k1 already contains cpulwp */
@@ -2656,7 +2656,7 @@
        REG_L   s7, CALLFRAME_SIZ+TF_REG_S7(sp)         # $23
        REG_L   s8, CALLFRAME_SIZ+TF_REG_S8(sp)         # $30
 #ifdef MIPS3_LOONGSON2
-       li      t0, (MIPS_DIAG_BTB_CLEAR|MIPS_DIAG_ITLB_CLEAR)
+       li      t0, (MIPS_DIAG_ITLB_CLEAR | MIPS_DIAG_BTB_CLEAR | MIPS_DIAG_RAS_DISABLE)
        mtc0    t0, MIPS_COP_0_DIAG
 #endif
 MIPSX(user_intr_return):