Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/arm/imx IPG clock is used instead of ENET_PLL clock...
details: https://anonhg.NetBSD.org/src/rev/c78c40dda34b
branches: trunk
changeset: 846325:c78c40dda34b
user: hkenken <hkenken%NetBSD.org@localhost>
date: Tue Nov 12 05:09:29 2019 +0000
description:
IPG clock is used instead of ENET_PLL clock to set MII Speed Control Register.
diffstat:
sys/arch/arm/imx/fdt/if_enet_imx.c | 16 +++++++++++++---
sys/arch/arm/imx/if_enet.c | 10 +++++-----
sys/arch/arm/imx/if_enet_imx6.c | 16 +++++++++++++---
sys/arch/arm/imx/if_enet_imx7.c | 8 ++++----
sys/arch/arm/imx/if_enetreg.h | 13 +++----------
sys/arch/arm/imx/if_enetvar.h | 5 +++--
6 files changed, 41 insertions(+), 27 deletions(-)
diffs (211 lines):
diff -r 17c3f94e54d6 -r c78c40dda34b sys/arch/arm/imx/fdt/if_enet_imx.c
--- a/sys/arch/arm/imx/fdt/if_enet_imx.c Tue Nov 12 04:32:36 2019 +0000
+++ b/sys/arch/arm/imx/fdt/if_enet_imx.c Tue Nov 12 05:09:29 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_enet_imx.c,v 1.4 2019/10/18 12:53:08 hkenken Exp $ */
+/* $NetBSD: if_enet_imx.c,v 1.5 2019/11/12 05:09:29 hkenken Exp $ */
/*-
* Copyright (c) 2019 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -25,7 +25,7 @@
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_enet_imx.c,v 1.4 2019/10/18 12:53:08 hkenken Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_enet_imx.c,v 1.5 2019/11/12 05:09:29 hkenken Exp $");
#include "opt_fdt.h"
@@ -90,6 +90,11 @@
return;
}
+ sc->sc_clk_ipg = fdtbus_clock_get(phandle, "ipg");
+ if (sc->sc_clk_enet == NULL) {
+ aprint_error(": couldn't get clock ipg\n");
+ goto failure;
+ }
sc->sc_clk_enet = fdtbus_clock_get(phandle, "ahb");
if (sc->sc_clk_enet == NULL) {
aprint_error(": couldn't get clock ahb\n");
@@ -149,7 +154,7 @@
aprint_normal_dev(self, "interrupting on %s\n", intrstr);
enet_init_clocks(sc);
- sc->sc_pllclock = clk_get_rate(sc->sc_clk_enet_ref);
+ sc->sc_clock = clk_get_rate(sc->sc_clk_ipg);
enet_phy_reset(efsc, phandle);
@@ -168,6 +173,11 @@
{
int error;
+ error = clk_enable(sc->sc_clk_ipg);
+ if (error) {
+ aprint_error_dev(sc->sc_dev, "couldn't enable ipg: %d\n", error);
+ return error;
+ }
error = clk_enable(sc->sc_clk_enet);
if (error) {
aprint_error_dev(sc->sc_dev, "couldn't enable enet: %d\n", error);
diff -r 17c3f94e54d6 -r c78c40dda34b sys/arch/arm/imx/if_enet.c
--- a/sys/arch/arm/imx/if_enet.c Tue Nov 12 04:32:36 2019 +0000
+++ b/sys/arch/arm/imx/if_enet.c Tue Nov 12 05:09:29 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_enet.c,v 1.27 2019/09/20 08:48:55 maxv Exp $ */
+/* $NetBSD: if_enet.c,v 1.28 2019/11/12 05:09:29 hkenken Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_enet.c,v 1.27 2019/09/20 08:48:55 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_enet.c,v 1.28 2019/11/12 05:09:29 hkenken Exp $");
#include "vlan.h"
@@ -1769,9 +1769,9 @@
ENET_REG_WRITE(sc, ENET_MIBC, ENET_MIBC_MIB_CLEAR);
ENET_REG_WRITE(sc, ENET_MIBC, 0);
- /* MII speed setup. MDCclk(=2.5MHz) = ENET_PLL/((val+1)*2) */
- val = ((sc->sc_pllclock) / 500000 - 1) / 10;
- ENET_REG_WRITE(sc, ENET_MSCR, val << 1);
+ /* MII speed setup. MDCclk(=2.5MHz) = (internal module clock)/((val+1)*2) */
+ val = (sc->sc_clock + (5000000 - 1)) / 5000000 - 1;
+ ENET_REG_WRITE(sc, ENET_MSCR, __SHIFTIN(val, ENET_MSCR_MII_SPEED));
/* Opcode/Pause Duration */
ENET_REG_WRITE(sc, ENET_OPD, 0x00010020);
diff -r 17c3f94e54d6 -r c78c40dda34b sys/arch/arm/imx/if_enet_imx6.c
--- a/sys/arch/arm/imx/if_enet_imx6.c Tue Nov 12 04:32:36 2019 +0000
+++ b/sys/arch/arm/imx/if_enet_imx6.c Tue Nov 12 05:09:29 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_enet_imx6.c,v 1.6 2019/07/30 06:26:31 hkenken Exp $ */
+/* $NetBSD: if_enet_imx6.c,v 1.7 2019/11/12 05:09:29 hkenken Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_enet_imx6.c,v 1.6 2019/07/30 06:26:31 hkenken Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_enet_imx6.c,v 1.7 2019/11/12 05:09:29 hkenken Exp $");
#include "locators.h"
#include "imxccm.h"
@@ -131,6 +131,11 @@
iomux_write(IMX6UL_IOMUX_GPR1, v);
}
+ sc->sc_clk_ipg = imx6_get_clock("enet");
+ if (sc->sc_clk_enet == NULL) {
+ aprint_error(": couldn't get clock ipg\n");
+ return;
+ }
sc->sc_clk_enet = imx6_get_clock("enet");
if (sc->sc_clk_enet == NULL) {
aprint_error(": couldn't get clock enet\n");
@@ -146,7 +151,7 @@
return;
}
- sc->sc_pllclock = clk_get_rate(sc->sc_clk_enet_ref);
+ sc->sc_clock = clk_get_rate(sc->sc_clk_ipg);
if (bus_space_map(sc->sc_iot, aa->aa_addr, aa->aa_size, 0,
&sc->sc_ioh)) {
@@ -179,6 +184,11 @@
{
int error;
+ error = clk_enable(sc->sc_clk_ipg);
+ if (error) {
+ aprint_error_dev(sc->sc_dev, "couldn't enable ipg: %d\n", error);
+ return error;
+ }
error = clk_enable(sc->sc_clk_enet);
if (error) {
aprint_error_dev(sc->sc_dev, "couldn't enable enet: %d\n", error);
diff -r 17c3f94e54d6 -r c78c40dda34b sys/arch/arm/imx/if_enet_imx7.c
--- a/sys/arch/arm/imx/if_enet_imx7.c Tue Nov 12 04:32:36 2019 +0000
+++ b/sys/arch/arm/imx/if_enet_imx7.c Tue Nov 12 05:09:29 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_enet_imx7.c,v 1.4 2019/07/30 06:26:31 hkenken Exp $ */
+/* $NetBSD: if_enet_imx7.c,v 1.5 2019/11/12 05:09:29 hkenken Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_enet_imx7.c,v 1.4 2019/07/30 06:26:31 hkenken Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_enet_imx7.c,v 1.5 2019/11/12 05:09:29 hkenken Exp $");
#include "locators.h"
#include "imxccm.h"
@@ -103,9 +103,9 @@
"couldn't enable CCM_ANALOG_PLL_ENET\n");
return;
}
- sc->sc_pllclock = imx7_get_clock(IMX7CLK_ENET_PLL);
+ sc->sc_clock = imx7_get_clock(IMX7CLK_IPG_CLK_ROOT);
#else
- sc->sc_pllclock = 1000000000;
+ sc->sc_clock = 66000000;
#endif
if (bus_space_map(sc->sc_iot, aa->aa_addr, aa->aa_size, 0,
diff -r 17c3f94e54d6 -r c78c40dda34b sys/arch/arm/imx/if_enetreg.h
--- a/sys/arch/arm/imx/if_enetreg.h Tue Nov 12 04:32:36 2019 +0000
+++ b/sys/arch/arm/imx/if_enetreg.h Tue Nov 12 05:09:29 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_enetreg.h,v 1.3 2017/06/09 18:14:59 ryo Exp $ */
+/* $NetBSD: if_enetreg.h,v 1.4 2019/11/12 05:09:29 hkenken Exp $ */
/*-
* Copyright (c) 2014 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -93,16 +93,9 @@
# define ENET_MMFR_PHY_REG(reg) __SHIFTIN(reg, __BITS(22, 18))
# define ENET_MMFR_DATAMASK 0x0000ffff
#define ENET_MSCR 0x00000044
-# define ENET_MSCR_HOLDTIME_1CLK 0x00000000
-# define ENET_MSCR_HOLDTIME_2CLK 0x00000100
-# define ENET_MSCR_HOLDTIME_3CLK 0x00000200
-# define ENET_MSCR_HOLDTIME_8CLK 0x00000700
+# define ENET_MSCR_HOLDTIME __BIT(10, 8)
# define ENET_MSCR_DIS_PRE __BIT(7)
-# define ENET_MSCR_MII_SPEED_25MHZ __SHIFTIN(4, __BITS(6, 1))
-# define ENET_MSCR_MII_SPEED_33MHZ __SHIFTIN(6, __BITS(6, 1))
-# define ENET_MSCR_MII_SPEED_40MHZ __SHIFTIN(7, __BITS(6, 1))
-# define ENET_MSCR_MII_SPEED_50MHZ __SHIFTIN(9, __BITS(6, 1))
-# define ENET_MSCR_MII_SPEED_66MHZ __SHIFTIN(13, __BITS(6, 1))
+# define ENET_MSCR_MII_SPEED __BITS(6, 1)
#define ENET_MIBC 0x00000064
# define ENET_MIBC_MIB_DIS __BIT(31)
diff -r 17c3f94e54d6 -r c78c40dda34b sys/arch/arm/imx/if_enetvar.h
--- a/sys/arch/arm/imx/if_enetvar.h Tue Nov 12 04:32:36 2019 +0000
+++ b/sys/arch/arm/imx/if_enetvar.h Tue Nov 12 05:09:29 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_enetvar.h,v 1.5 2019/09/13 07:55:06 msaitoh Exp $ */
+/* $NetBSD: if_enetvar.h,v 1.6 2019/11/12 05:09:29 hkenken Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -58,8 +58,9 @@
int sc_unit;
int sc_imxtype;
int sc_rgmii;
- unsigned int sc_pllclock;
+ unsigned int sc_clock;
+ struct clk *sc_clk_ipg;
struct clk *sc_clk_enet;
struct clk *sc_clk_enet_ref;
Home |
Main Index |
Thread Index |
Old Index