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[src/trunk]: src/sys/arch/arm/amlogic Add Amlogic Meson RTC driver (FDT version)



details:   https://anonhg.NetBSD.org/src/rev/bf21a6eacc11
branches:  trunk
changeset: 838500:bf21a6eacc11
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sun Jan 20 17:58:22 2019 +0000

description:
Add Amlogic Meson RTC driver (FDT version)

diffstat:

 sys/arch/arm/amlogic/files.meson    |    8 +-
 sys/arch/arm/amlogic/meson_rtc.c    |  386 ++++++++++++++++++++++++++++++++++++
 sys/arch/arm/amlogic/meson_rtcreg.h |  101 +++++++++
 3 files changed, 491 insertions(+), 4 deletions(-)

diffs (truncated from 517 to 300 lines):

diff -r dbf9e539490a -r bf21a6eacc11 sys/arch/arm/amlogic/files.meson
--- a/sys/arch/arm/amlogic/files.meson  Sun Jan 20 17:57:29 2019 +0000
+++ b/sys/arch/arm/amlogic/files.meson  Sun Jan 20 17:58:22 2019 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: files.meson,v 1.3 2019/01/20 00:44:01 jmcneill Exp $
+#      $NetBSD: files.meson,v 1.4 2019/01/20 17:58:22 jmcneill Exp $
 #
 # Configuration info for Amlogic Meson family SoCs
 #
@@ -58,9 +58,9 @@
 file   arch/arm/amlogic/meson_usbphy.c         meson_usbphy
 
 # RTC
-#device        mesonrtc
-#attach        mesonrtc at fdt with meson_rtc
-#file  arch/arm/amlogic/meson_rtc.c            meson_rtc
+device mesonrtc
+attach mesonrtc at fdt with meson_rtc
+file   arch/arm/amlogic/meson_rtc.c            meson_rtc
 
 # RNG
 device mesonrng
diff -r dbf9e539490a -r bf21a6eacc11 sys/arch/arm/amlogic/meson_rtc.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/amlogic/meson_rtc.c  Sun Jan 20 17:58:22 2019 +0000
@@ -0,0 +1,386 @@
+/* $NetBSD: meson_rtc.c,v 1.1 2019/01/20 17:58:22 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: meson_rtc.c,v 1.1 2019/01/20 17:58:22 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/atomic.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+
+#include <dev/clock_subr.h>
+
+#include <arm/amlogic/meson_rtcreg.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#define RESET_RETRY_TIMES      3
+#define RTC_COMM_DELAY         5
+#define RTC_RESET_DELAY                100
+#define RTC_STATIC_VALUE_INIT  0x180a  /* XXX: MAGIC? */
+
+struct meson_rtc_softc {
+       device_t                sc_dev;
+       bus_space_tag_t         sc_bst;
+       bus_space_handle_t      sc_bsh;
+       struct todr_chip_handle sc_todr;
+       int                     sc_osc_failed;
+       unsigned int            sc_busy;
+};
+
+static const char * const compatible[] = {
+       "amlogic,meson8b-rtc",
+       NULL
+};
+
+static int meson_rtc_match(device_t, cfdata_t, void *);
+static void meson_rtc_attach(device_t, device_t, void *);
+static int meson_rtc_todr_gettime(todr_chip_handle_t, struct timeval *);
+static int meson_rtc_todr_settime(todr_chip_handle_t, struct timeval *);
+
+CFATTACH_DECL_NEW(meson_rtc, sizeof(struct meson_rtc_softc),
+       meson_rtc_match, meson_rtc_attach, NULL, NULL);
+
+#define RTC_WRITE(sc, reg, val) \
+       bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+#define RTC_READ(sc, reg) \
+       bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+
+static inline void
+setbits(struct meson_rtc_softc *sc, uint32_t reg, uint32_t bits)
+{
+
+       RTC_WRITE(sc, reg, RTC_READ(sc, reg) | bits);
+}
+
+static inline void
+clrbits(struct meson_rtc_softc *sc, uint32_t reg, uint32_t bits)
+{
+
+       RTC_WRITE(sc, reg, RTC_READ(sc, reg) & ~bits);
+}
+
+static int
+meson_rtc_check_osc_clk(struct meson_rtc_softc *sc)
+{
+       uint32_t cnt1, cnt2;
+
+       setbits(sc, AO_RTC_REG3, AO_RTC_REG3_COUNT_ALWAYS);
+
+       /*
+        * Wait for 50uS.  32.768khz is 30.5uS.  This should be long
+        * enough for one full cycle of 32.768 khz.
+        */
+       cnt1 = RTC_READ(sc, AO_RTC_REG2);
+       delay(50);
+       cnt2 = RTC_READ(sc, AO_RTC_REG2);
+
+       clrbits(sc, AO_RTC_REG3, AO_RTC_REG3_COUNT_ALWAYS);
+
+       return cnt1 == cnt2;
+}
+
+static int
+meson_rtc_match(device_t parent, cfdata_t cf, void *aux)
+{
+       struct fdt_attach_args * const faa = aux;
+
+       return of_match_compatible(faa->faa_phandle, compatible);
+}
+
+static void
+meson_rtc_attach(device_t parent, device_t self, void *aux)
+{
+       struct meson_rtc_softc * const sc = device_private(self);
+       struct fdt_attach_args * const faa = aux;
+       const int phandle = faa->faa_phandle;
+       bus_addr_t addr;
+       bus_size_t size;
+
+       if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
+               aprint_error(": couldn't map registers\n");
+               return;
+       }
+
+       sc->sc_dev = self;
+       sc->sc_bst = faa->faa_bst;
+       if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
+               aprint_error(": couldn't map registers\n");
+               return;
+       }
+
+       sc->sc_osc_failed = meson_rtc_check_osc_clk(sc);
+
+       memset(&sc->sc_todr, 0, sizeof(sc->sc_todr));
+       sc->sc_todr.cookie = sc;
+       sc->sc_todr.todr_gettime = meson_rtc_todr_gettime;
+       sc->sc_todr.todr_settime = meson_rtc_todr_settime;
+
+       aprint_naive("\n");
+       aprint_normal(": RTC");
+       if (sc->sc_osc_failed) {
+               aprint_normal(" battery not present or discharged\n");
+       } else {
+               aprint_normal("\n");
+               todr_attach(&sc->sc_todr);
+       }
+}
+
+static void
+meson_rtc_sclk_pulse(struct meson_rtc_softc *sc)
+{
+
+       delay(RTC_COMM_DELAY);
+       setbits(sc, AO_RTC_REG0, AO_RTC_REG0_SCLK);
+
+       delay(RTC_COMM_DELAY);
+       clrbits(sc, AO_RTC_REG0, AO_RTC_REG0_SCLK);
+}
+
+static void
+meson_rtc_send_bit(struct meson_rtc_softc *sc, uint32_t bitset)
+{
+
+       if (bitset)
+               setbits(sc, AO_RTC_REG0, AO_RTC_REG0_SDI);
+       else
+               clrbits(sc, AO_RTC_REG0, AO_RTC_REG0_SDI);
+
+       meson_rtc_sclk_pulse(sc);
+}
+
+#define SERIAL_ADDR_BITS       3
+#define SERIAL_DATA_BITS       32
+#define        SERIAL_TYPE_ADDR        (1 << (SERIAL_ADDR_BITS - 1))
+#define        SERIAL_TYPE_DATA        (1 << (SERIAL_DATA_BITS - 1))
+
+static void
+meson_rtc_send_data(struct meson_rtc_softc *sc,
+    uint32_t nextbit, uint32_t data)
+{
+
+       KASSERT(nextbit == SERIAL_TYPE_ADDR || nextbit == SERIAL_TYPE_DATA);
+
+       while (nextbit) {
+               meson_rtc_send_bit(sc, data & nextbit);
+               nextbit >>= 1;
+       }
+}
+
+static uint32_t
+meson_rtc_get_data(struct meson_rtc_softc *sc)
+{
+       uint32_t data;
+       size_t i;
+
+       data = 0;
+       for (i = 0; i < SERIAL_DATA_BITS; i++) {
+               meson_rtc_sclk_pulse(sc);
+               data <<= 1;
+               data |= __SHIFTOUT(RTC_READ(sc, AO_RTC_REG1), AO_RTC_REG1_SDO);
+       }
+       return data;
+}
+
+enum serial_mode {
+       SERIAL_MODE_READ,
+       SERIAL_MODE_WRITE,
+};
+
+static void
+meson_rtc_set_mode(struct meson_rtc_softc *sc, enum serial_mode mode)
+{
+
+       clrbits(sc, AO_RTC_REG0, AO_RTC_REG0_SEN);
+
+       switch(mode) {
+       case SERIAL_MODE_READ:
+               clrbits(sc, AO_RTC_REG0, AO_RTC_REG0_SDI);
+               break;
+       case SERIAL_MODE_WRITE:
+               setbits(sc, AO_RTC_REG0, AO_RTC_REG0_SDI);
+               break;
+       default:
+               KASSERT(1);
+               return;
+       }
+       meson_rtc_sclk_pulse(sc);
+
+       clrbits(sc, AO_RTC_REG0, AO_RTC_REG0_SDI);
+}
+
+static int
+meson_rtc_wait_s_ready(struct meson_rtc_softc *sc)
+{
+       size_t s_nrdy_cnt, retry_cnt;
+
+       s_nrdy_cnt = 40000;
+       retry_cnt = 0;
+       while (!(RTC_READ(sc, AO_RTC_REG1) & AO_RTC_REG1_S_READY)) {
+               if (s_nrdy_cnt-- == 0) {
+                       s_nrdy_cnt = 40000;
+                       if (retry_cnt++ == RESET_RETRY_TIMES)
+                               return 0;
+                       /* XXX: reset_s_ready?  Linux does not. */
+                       setbits(sc, AO_RTC_REG1, AO_RTC_REG1_S_READY);
+                       delay(RTC_RESET_DELAY);
+               }
+       }
+       return 1;
+}
+
+static int
+meson_rtc_comm_init(struct meson_rtc_softc *sc)
+{
+
+       clrbits(sc, AO_RTC_REG0,
+           AO_RTC_REG0_SEN | AO_RTC_REG0_SCLK | AO_RTC_REG0_SDI);
+
+       if (meson_rtc_wait_s_ready(sc)) {
+               setbits(sc, AO_RTC_REG0, AO_RTC_REG0_SEN);
+               return 0;
+       }
+       return -1;
+}
+
+static void
+meson_rtc_static_register_write(struct meson_rtc_softc *sc, uint32_t data)



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