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[src/trunk]: src Drop support for 586 PMCs; the detection is broken, and I'm ...
details: https://anonhg.NetBSD.org/src/rev/0340cfec8805
branches: trunk
changeset: 822550:0340cfec8805
user: maxv <maxv%NetBSD.org@localhost>
date: Fri Mar 24 18:30:44 2017 +0000
description:
Drop support for 586 PMCs; the detection is broken, and I'm not sure the
code even works. No one has ever cared about this anyway, and we won't
maintain it.
While here, fix the mask on the counter - K7 and F10H have 48bit counters.
diffstat:
sys/arch/x86/x86/pmc.c | 105 +++++++++++++++++++-----------------------------
usr.bin/pmc/pmc.c | 47 +---------------------
2 files changed, 44 insertions(+), 108 deletions(-)
diffs (238 lines):
diff -r 69569ecc6600 -r 0340cfec8805 sys/arch/x86/x86/pmc.c
--- a/sys/arch/x86/x86/pmc.c Fri Mar 24 18:03:32 2017 +0000
+++ b/sys/arch/x86/x86/pmc.c Fri Mar 24 18:30:44 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmc.c,v 1.3 2017/03/11 14:13:39 maxv Exp $ */
+/* $NetBSD: pmc.c,v 1.4 2017/03/24 18:30:44 maxv Exp $ */
/*
* Copyright (c) 2017 The NetBSD Foundation, Inc.
@@ -67,7 +67,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmc.c,v 1.3 2017/03/11 14:13:39 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmc.c,v 1.4 2017/03/24 18:30:44 maxv Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -89,6 +89,8 @@
uint64_t evtval; /* event selector value */
uint32_t ctrmsr; /* counter MSR */
uint64_t ctrval; /* initial counter value */
+ uint64_t ctrmaxval; /* maximal counter value */
+ uint64_t ctrmask;
} pmc_state_t;
static x86_pmc_cpuval_t pmc_val_cpus[MAXCPUS] __aligned(CACHE_LINE_SIZE);
@@ -104,9 +106,7 @@
pmc_state_t *pmc = (pmc_state_t *)arg1;
struct cpu_info *ci = curcpu();
- pmc_val_cpus[cpu_index(ci)].ctrval =
- rdmsr(pmc->ctrmsr) & 0xffffffffffULL;
- pmc_val_cpus[cpu_index(ci)].overfl = 0;
+ pmc_val_cpus[cpu_index(ci)].ctrval = rdmsr(pmc->ctrmsr) & pmc->ctrmask;
}
static void
@@ -126,11 +126,6 @@
wrmsr(pmc->ctrmsr, pmc->ctrval);
switch (pmc_type) {
- case PMC_TYPE_I586:
- wrmsr(MSR_CESR, pmc_state[0].evtval |
- (pmc_state[1].evtval << 16));
- break;
-
case PMC_TYPE_I686:
case PMC_TYPE_K7:
case PMC_TYPE_F10H:
@@ -167,13 +162,6 @@
* Initialize the event MSR.
*/
switch (pmc_type) {
- case PMC_TYPE_I586:
- pmc->evtval = args->event |
- ((args->flags & PMC_SETUP_KERNEL) ? PMC5_CESR_OS : 0) |
- ((args->flags & PMC_SETUP_USER) ? PMC5_CESR_USR : 0) |
- ((args->flags & PMC_SETUP_EDGE) ? PMC5_CESR_E : 0);
- break;
-
case PMC_TYPE_I686:
pmc->evtval = args->event | PMC6_EVTSEL_EN |
(args->unit << PMC6_EVTSEL_UNIT_SHIFT) |
@@ -233,61 +221,52 @@
{
const char *cpu_vendorstr;
struct cpu_info *ci;
+ size_t i;
pmc_type = PMC_TYPE_NONE;
+ if (cpu_class != CPUCLASS_686)
+ return;
+
ci = curcpu();
cpu_vendorstr = (char *)ci->ci_vendor;
- switch (cpu_class) {
- case CPUCLASS_586:
- if (strncmp(cpu_vendorstr, "GenuineIntel", 12) == 0) {
- pmc_type = PMC_TYPE_I586;
- pmc_ncounters = 2;
- pmc_state[0].ctrmsr = MSR_CTR0;
- pmc_state[1].ctrmsr = MSR_CTR1;
- break;
+ if (strncmp(cpu_vendorstr, "GenuineIntel", 12) == 0) {
+ /* Right now we're missing Pentium 4 support. */
+ if (cpuid_level == -1 ||
+ CPUID_TO_FAMILY(ci->ci_signature) == CPU_FAMILY_P4)
+ return;
+ pmc_type = PMC_TYPE_I686;
+ pmc_ncounters = 2;
+ for (i = 0; i < pmc_ncounters; i++) {
+ pmc_state[i].evtmsr = MSR_EVNTSEL0 + i;
+ pmc_state[i].ctrmsr = MSR_PERFCTR0 + i;
+ pmc_state[i].ctrmaxval = (UINT64_C(1) << 40) - 1;
+ pmc_state[i].ctrmask = 0xFFFFFFFFFFULL;
}
-
- case CPUCLASS_686:
- if (strncmp(cpu_vendorstr, "GenuineIntel", 12) == 0) {
- /* Right now we're missing Pentium 4 support. */
- if (cpuid_level == -1 ||
- CPUID_TO_FAMILY(ci->ci_signature) == CPU_FAMILY_P4)
- break;
- pmc_type = PMC_TYPE_I686;
- pmc_ncounters = 2;
- pmc_state[0].evtmsr = MSR_EVNTSEL0;
- pmc_state[0].ctrmsr = MSR_PERFCTR0;
- pmc_state[1].evtmsr = MSR_EVNTSEL1;
- pmc_state[1].ctrmsr = MSR_PERFCTR1;
- } else if (strncmp(cpu_vendorstr, "AuthenticAMD", 12) == 0) {
- if (CPUID_TO_FAMILY(ci->ci_signature) == 0x10) {
- pmc_type = PMC_TYPE_F10H;
- pmc_ncounters = 4;
- pmc_state[0].evtmsr = MSR_F10H_EVNTSEL0;
- pmc_state[0].ctrmsr = MSR_F10H_PERFCTR0;
- pmc_state[1].evtmsr = MSR_F10H_EVNTSEL1;
- pmc_state[1].ctrmsr = MSR_F10H_PERFCTR1;
- pmc_state[2].evtmsr = MSR_F10H_EVNTSEL2;
- pmc_state[2].ctrmsr = MSR_F10H_PERFCTR2;
- pmc_state[3].evtmsr = MSR_F10H_EVNTSEL3;
- pmc_state[3].ctrmsr = MSR_F10H_PERFCTR3;
- } else {
- /* XXX: make sure it is at least K7 */
- pmc_type = PMC_TYPE_K7;
- pmc_ncounters = 4;
- pmc_state[0].evtmsr = MSR_K7_EVNTSEL0;
- pmc_state[0].ctrmsr = MSR_K7_PERFCTR0;
- pmc_state[1].evtmsr = MSR_K7_EVNTSEL1;
- pmc_state[1].ctrmsr = MSR_K7_PERFCTR1;
- pmc_state[2].evtmsr = MSR_K7_EVNTSEL2;
- pmc_state[2].ctrmsr = MSR_K7_PERFCTR2;
- pmc_state[3].evtmsr = MSR_K7_EVNTSEL3;
- pmc_state[3].ctrmsr = MSR_K7_PERFCTR3;
+ } else if (strncmp(cpu_vendorstr, "AuthenticAMD", 12) == 0) {
+ if (CPUID_TO_FAMILY(ci->ci_signature) == 0x10) {
+ pmc_type = PMC_TYPE_F10H;
+ pmc_ncounters = 4;
+ for (i = 0; i < pmc_ncounters; i++) {
+ pmc_state[i].evtmsr = MSR_F10H_EVNTSEL0 + i;
+ pmc_state[i].ctrmsr = MSR_F10H_PERFCTR0 + i;
+ pmc_state[i].ctrmaxval =
+ (UINT64_C(1) << 48) - 1;
+ pmc_state[i].ctrmask = 0xFFFFFFFFFFFFULL;
+ }
+ } else {
+ /* XXX: make sure it is at least K7 */
+ pmc_type = PMC_TYPE_K7;
+ pmc_ncounters = 4;
+ for (i = 0; i < pmc_ncounters; i++) {
+ pmc_state[i].evtmsr = MSR_K7_EVNTSEL0 + i;
+ pmc_state[i].ctrmsr = MSR_K7_PERFCTR0 + i;
+ pmc_state[i].ctrmaxval =
+ (UINT64_C(1) << 48) - 1;
+ pmc_state[i].ctrmask = 0xFFFFFFFFFFFFULL;
}
}
- break;
}
mutex_init(&pmc_lock, MUTEX_DEFAULT, IPL_NONE);
diff -r 69569ecc6600 -r 0340cfec8805 usr.bin/pmc/pmc.c
--- a/usr.bin/pmc/pmc.c Fri Mar 24 18:03:32 2017 +0000
+++ b/usr.bin/pmc/pmc.c Fri Mar 24 18:30:44 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmc.c,v 1.22 2017/03/11 10:33:46 maxv Exp $ */
+/* $NetBSD: pmc.c,v 1.23 2017/03/24 18:30:44 maxv Exp $ */
/*
* Copyright (c) 2017 The NetBSD Foundation, Inc.
@@ -66,7 +66,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: pmc.c,v 1.22 2017/03/11 10:33:46 maxv Exp $");
+__RCSID("$NetBSD: pmc.c,v 1.23 2017/03/24 18:30:44 maxv Exp $");
#endif
#include <inttypes.h>
@@ -106,47 +106,6 @@
size_t size;
} pmc_name2val_cpu_t;
-static const pmc_name2val_t i586_names[] = {
- { "tlb-data-miss", PMC5_DATA_TLB_MISS, 0 },
- { "tlb-ins-miss", PMC5_INST_TLB_MISS, 0 },
- { "l1cache-ins-miss", PMC5_INST_CACHE_MISS, 0 },
- { "l1cache-data-miss", PMC5_DATA_RW_MISS, 0 },
- { "l1cache-data-miss-read", PMC5_DATA_READ_MISS, 0 },
- { "l1cache-data-miss-write", PMC5_DATA_WRITE_MISS, 0 },
- { "l1cache-writeback", PMC5_DATA_LINES_WBACK, 0 },
- { "l1cache-writeback-hit", PMC5_WRITE_M_E, 0 },
- { "l2cache-data-snoop", PMC5_DATA_CACHE_SNOOP, 0 },
- { "l2cache-data-snoop-hit", PMC5_DATA_CACHE_SNOOP_HIT, 0 },
- { "mem-read", PMC5_DATA_READ, 0 },
- { "mem-write", PMC5_DATA_WRITE, 0 },
- { "mem-access", PMC5_DATA_RW, 0 },
- { "mem-access-both-pipes", PMC5_MEM_ACCESS_BOTH_PIPES, 0 },
- { "mem-bank-conflicts", PMC5_BANK_CONFLICTS, 0 },
- { "mem-misalign-ref", PMC5_MISALIGNED_DATA, 0 },
- { "mem-uncached-read", PMC5_NONCACHE_MEM_READ, 0 },
- { "seg-load-any", PMC5_SEGMENT_REG_LOAD, 0 },
- { "branch", PMC5_BRANCHES, 0 },
- { "branch-btb-hit", PMC5_BTB_HITS, 0 },
- { "branch-taken", PMC5_BRANCH_TAKEN, 0 },
- { "ins-read", PMC5_INST_READ, 0 },
- { "ins-pipeline-flush", PMC5_PIPELINE_FLUSH, 0 },
- { "ins-executed", PMC5_INST_EXECUTED, 0 },
- { "ins-executed-vpipe", PMC5_INST_EXECUTED_V_PIPE, 0 },
- { "ins-stall-agi", PMC5_AGI_STALL, 0 },
- { "ins-stall-write", PMC5_WRITE_BACKUP_STALL, 0 },
- { "ins-stall-data", PMC5_DATA_READ_STALL, 0 },
- { "ins-stall-writeline", PMC5_WRITE_E_M_STALL, 0 },
- { "bus-utilization", PMC5_BUS_UTILIZATION, 0 },
- { "bus-locked", PMC5_LOCKED_BUS, 0 },
- { "bus-io-cycle", PMC5_IO_CYCLE, 0 },
- { "fpu-flops", PMC5_FLOPS, 0 },
- { "int-hw", PMC5_HARDWARE_INTR, 0 },
- { "break-match0", PMC5_BP0_MATCH, 0 },
- { "break-match1", PMC5_BP1_MATCH, 0 },
- { "break-match2", PMC5_BP2_MATCH, 0 },
- { "break-match3", PMC5_BP3_MATCH, 0 },
-};
-
static const pmc_name2val_t i686_names[] = {
{ "mem-refs", PMC6_DATA_MEM_REFS, 0 },
{ "l1cache-lines", PMC6_DCU_LINES_IN, 0 },
@@ -395,8 +354,6 @@
};
static const pmc_name2val_cpu_t pmc_cpus[] = {
- { PMC_TYPE_I586, i586_names,
- sizeof(i586_names) / sizeof(pmc_name2val_t) },
{ PMC_TYPE_I686, i686_names,
sizeof(i686_names) / sizeof(pmc_name2val_t) },
{ PMC_TYPE_K7, k7_names,
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