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[src/trunk]: src/sys/arch Work in progress HDMI / framebuffer support for Teg...
details: https://anonhg.NetBSD.org/src/rev/f502fb887507
branches: trunk
changeset: 808472:f502fb887507
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Mon May 18 19:32:48 2015 +0000
description:
Work in progress HDMI / framebuffer support for Tegra K1.
diffstat:
sys/arch/arm/nvidia/files.tegra | 16 +-
sys/arch/arm/nvidia/tegra_car.c | 98 +++++++-
sys/arch/arm/nvidia/tegra_carreg.h | 48 +++-
sys/arch/arm/nvidia/tegra_dc.c | 354 ++++++++++++++++++++++++++++
sys/arch/arm/nvidia/tegra_dcreg.h | 421 ++++++++++++++++++++++++++++++++++
sys/arch/arm/nvidia/tegra_genfb.c | 191 +++++++++++++++
sys/arch/arm/nvidia/tegra_hdmi.c | 352 ++++++++++++++++++++++++++++
sys/arch/arm/nvidia/tegra_hdmireg.h | 280 ++++++++++++++++++++++
sys/arch/arm/nvidia/tegra_io.c | 15 +-
sys/arch/arm/nvidia/tegra_var.h | 22 +-
sys/arch/evbarm/conf/JETSONTK1 | 24 +-
sys/arch/evbarm/tegra/tegra_machdep.c | 31 ++-
12 files changed, 1842 insertions(+), 10 deletions(-)
diffs (truncated from 2063 to 300 lines):
diff -r 982588e6cce0 -r f502fb887507 sys/arch/arm/nvidia/files.tegra
--- a/sys/arch/arm/nvidia/files.tegra Mon May 18 17:49:16 2015 +0000
+++ b/sys/arch/arm/nvidia/files.tegra Mon May 18 19:32:48 2015 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.tegra,v 1.11 2015/05/15 11:49:10 jmcneill Exp $
+# $NetBSD: files.tegra,v 1.12 2015/05/18 19:32:48 jmcneill Exp $
#
# Configuration info for NVIDIA Tegra ARM Peripherals
#
@@ -87,6 +87,20 @@
attach hdaudio at tegraio with tegra_hdaudio
file arch/arm/nvidia/tegra_hdaudio.c tegra_hdaudio
+# Display controller
+device tegradc { }
+attach tegradc at tegraio with tegra_dc
+file arch/arm/nvidia/tegra_dc.c tegra_dc
+
+# Framebuffer console
+attach genfb at tegradc with tegra_genfb
+file arch/arm/nvidia/tegra_genfb.c tegra_genfb
+
+# HDMI
+device tegrahdmi: edid, ddc_read_edid, videomode
+attach tegrahdmi at tegraio with tegra_hdmi
+file arch/arm/nvidia/tegra_hdmi.c tegra_hdmi
+
# Console parameters
defparam opt_tegra.h CONADDR
defparam opt_tegra.h CONSPEED
diff -r 982588e6cce0 -r f502fb887507 sys/arch/arm/nvidia/tegra_car.c
--- a/sys/arch/arm/nvidia/tegra_car.c Mon May 18 17:49:16 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_car.c Mon May 18 19:32:48 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_car.c,v 1.15 2015/05/16 23:07:51 jmcneill Exp $ */
+/* $NetBSD: tegra_car.c,v 1.16 2015/05/18 19:32:48 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
#include "locators.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.15 2015/05/16 23:07:51 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.16 2015/05/18 19:32:48 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -52,6 +52,8 @@
bus_space_handle_t sc_bsh;
};
+static void tegra_car_init(struct tegra_car_softc *);
+
static struct tegra_car_softc *pmc_softc = NULL;
CFATTACH_DECL_NEW(tegra_car, sizeof(struct tegra_car_softc),
@@ -81,11 +83,28 @@
aprint_naive("\n");
aprint_normal(": CAR\n");
+ tegra_car_init(sc);
+
aprint_verbose_dev(self, "PLLX = %u Hz\n", tegra_car_pllx_rate());
aprint_verbose_dev(self, "PLLC = %u Hz\n", tegra_car_pllc_rate());
aprint_verbose_dev(self, "PLLE = %u Hz\n", tegra_car_plle_rate());
aprint_verbose_dev(self, "PLLU = %u Hz\n", tegra_car_pllu_rate());
aprint_verbose_dev(self, "PLLP0 = %u Hz\n", tegra_car_pllp0_rate());
+ aprint_verbose_dev(self, "PLLD2 = %u Hz\n", tegra_car_plld2_rate());
+}
+
+static void
+tegra_car_init(struct tegra_car_softc *sc)
+{
+ bus_space_tag_t bst = sc->sc_bst;
+ bus_space_handle_t bsh = sc->sc_bsh;
+
+ tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG,
+ __SHIFTIN(1, CAR_PLLD2_BASE_MDIV) |
+ __SHIFTIN(99, CAR_PLLD2_BASE_NDIV) |
+ __SHIFTIN(2, CAR_PLLD2_BASE_PLDIV),
+ CAR_PLLD2_BASE_REF_SRC_SEL |
+ CAR_PLLD2_BASE_PLDIV | CAR_PLLD2_BASE_NDIV | CAR_PLLD2_BASE_MDIV);
}
static void
@@ -220,6 +239,13 @@
}
u_int
+tegra_car_plld2_rate(void)
+{
+ return tegra_car_pll_rate(CAR_PLLD2_BASE_REG, CAR_PLLD2_BASE_MDIV,
+ CAR_PLLD2_BASE_NDIV, CAR_PLLD2_BASE_PLDIV);
+}
+
+u_int
tegra_car_uart_rate(u_int port)
{
bus_space_tag_t bst;
@@ -577,3 +603,71 @@
return 0;
}
+
+void
+tegra_car_hdmi_enable(u_int rate)
+{
+ bus_space_tag_t bst;
+ bus_space_handle_t bsh;
+
+ tegra_car_get_bs(&bst, &bsh);
+
+ /* Enter reset, enable clock */
+ bus_space_write_4(bst, bsh, CAR_RST_DEV_H_SET_REG, CAR_DEV_H_HDMI);
+ bus_space_write_4(bst, bsh, CAR_CLK_ENB_H_SET_REG, CAR_DEV_H_HDMI);
+
+ /* Change IDDQ from 1 to 0 */
+ tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG,
+ 0, CAR_PLLD2_BASE_IDDQ);
+ delay(2);
+ /* Enable PLLD2 */
+ tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG,
+ CAR_PLLD2_BASE_ENABLE, 0);
+
+ /* Set clock source to PLLD2 */
+ const u_int div = howmany(tegra_car_plld2_rate(), rate);;
+ bus_space_write_4(bst, bsh, CAR_CLKSRC_HDMI_REG,
+ __SHIFTIN(CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0, CAR_CLKSRC_HDMI_SRC) |
+ __SHIFTIN(div - 1, CAR_CLKSRC_HDMI_DIV));
+
+ /* Leave reset */
+ bus_space_write_4(bst, bsh, CAR_RST_DEV_H_CLR_REG, CAR_DEV_H_HDMI);
+}
+
+int
+tegra_car_dc_enable(u_int port)
+{
+ bus_space_tag_t bst;
+ bus_space_handle_t bsh;
+ bus_size_t src_reg;
+ uint32_t dev_bit;
+
+ tegra_car_get_bs(&bst, &bsh);
+
+ switch (port) {
+ case 0:
+ dev_bit = CAR_DEV_L_DISP1;
+ src_reg = CAR_CLKSRC_DISP1_REG;
+ break;
+ case 1:
+ dev_bit = CAR_DEV_L_DISP2;
+ src_reg = CAR_CLKSRC_DISP2_REG;
+ break;
+ default:
+ return EINVAL;
+ }
+
+ /* Enter reset, enable clock */
+ bus_space_write_4(bst, bsh, CAR_RST_DEV_L_SET_REG, dev_bit);
+ bus_space_write_4(bst, bsh, CAR_CLK_ENB_L_SET_REG, dev_bit);
+
+ /* Select PLLP for clock source */
+ bus_space_write_4(bst, bsh, src_reg,
+ __SHIFTIN(CAR_CLKSRC_DISP_SRC_PLLP_OUT0,
+ CAR_CLKSRC_DISP_SRC));
+
+ /* Leave reset */
+ bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, dev_bit);
+
+ return 0;
+}
diff -r 982588e6cce0 -r f502fb887507 sys/arch/arm/nvidia/tegra_carreg.h
--- a/sys/arch/arm/nvidia/tegra_carreg.h Mon May 18 17:49:16 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_carreg.h Mon May 18 19:32:48 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_carreg.h,v 1.14 2015/05/14 10:23:03 jmcneill Exp $ */
+/* $NetBSD: tegra_carreg.h,v 1.15 2015/05/18 19:32:48 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -104,6 +104,30 @@
#define CAR_PLLE_MISC_REG 0xec
+#define CAR_PLLD2_BASE_REG 0x4b8
+#define CAR_PLLD2_BASE_BYPASS __BIT(31)
+#define CAR_PLLD2_BASE_ENABLE __BIT(30)
+#define CAR_PLLD2_BASE_REF_DIS __BIT(29)
+#define CAR_PLLD2_BASE_FREQLOCK __BIT(28)
+#define CAR_PLLD2_BASE_LOCK __BIT(27)
+#define CAR_PLLD2_BASE_REF_SRC_SEL __BITS(26,25)
+#define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D 0
+#define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D2 1
+#define CAR_PLLD2_BASE_LOCK_OVERRIDE __BIT(24)
+#define CAR_PLLD2_BASE_PLDIV __BITS(23,20)
+#define CAR_PLLD2_BASE_IDDQ __BIT(19)
+#define CAR_PLLD2_BASE_PTS __BIT(16)
+#define CAR_PLLD2_BASE_NDIV __BITS(15,8)
+#define CAR_PLLD2_BASE_MDIV __BITS(7,0)
+
+#define CAR_PLLD2_MISC_REG 0x4bc
+#define CAR_PLLD2_MISC_EN_FSTLCK __BIT(31)
+#define CAR_PLLD2_MISC_LOCK_ENABLE __BIT(30)
+#define CAR_PLLD2_MISC_MON_TEST_OUT __BITS(29,27)
+#define CAR_PLLD2_MISC_KCP __BITS(26,25)
+#define CAR_PLLD2_MISC_KVCO __BIT(24)
+#define CAR_PLLD2_MISC_SETUP __BITS(23,0)
+
#define CAR_CLKSRC_I2C1_REG 0x124
#define CAR_CLKSRC_I2C2_REG 0x198
#define CAR_CLKSRC_I2C3_REG 0x1b8
@@ -150,6 +174,28 @@
#define CAR_CLKSRC_SDMMC_SRC_CLK_M 6
#define CAR_CLKSRC_SDMMC_DIV __BITS(7,0)
+#define CAR_CLKSRC_HDMI_REG 0x18c
+#define CAR_CLKSRC_HDMI_SRC __BITS(31,29)
+#define CAR_CLKSRC_HDMI_SRC_PLLP_OUT0 0
+#define CAR_CLKSRC_HDMI_SRC_PLLM_OUT0 1
+#define CAR_CLKSRC_HDMI_SRC_PLLD_OUT0 2
+#define CAR_CLKSRC_HDMI_SRC_PLLA_OUT0 3
+#define CAR_CLKSRC_HDMI_SRC_PLLC_OUT0 4
+#define CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0 5
+#define CAR_CLKSRC_HDMI_SRC_CLK_M 6
+#define CAR_CLKSRC_HDMI_DIV __BITS(7,0)
+
+#define CAR_CLKSRC_DISP1_REG 0x138
+#define CAR_CLKSRC_DISP2_REG 0x13c
+#define CAR_CLKSRC_DISP_SRC __BITS(31,29)
+#define CAR_CLKSRC_DISP_SRC_PLLP_OUT0 0
+#define CAR_CLKSRC_DISP_SRC_PLLM_OUT0 1
+#define CAR_CLKSRC_DISP_SRC_PLLD_OUT0 2
+#define CAR_CLKSRC_DISP_SRC_PLLA_OUT0 3
+#define CAR_CLKSRC_DISP_SRC_PLLC_OUT0 4
+#define CAR_CLKSRC_DISP_SRC_PLLD2_OUT0 5
+#define CAR_CLKSRC_DISP_SRC_CLK_M 6
+
#define CAR_RST_DEV_L_SET_REG 0x300
#define CAR_RST_DEV_L_CLR_REG 0x304
#define CAR_RST_DEV_H_SET_REG 0x308
diff -r 982588e6cce0 -r f502fb887507 sys/arch/arm/nvidia/tegra_dc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/nvidia/tegra_dc.c Mon May 18 19:32:48 2015 +0000
@@ -0,0 +1,354 @@
+/* $NetBSD: tegra_dc.c,v 1.1 2015/05/18 19:32:48 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "locators.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: tegra_dc.c,v 1.1 2015/05/18 19:32:48 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+
+#include <dev/videomode/videomode.h>
+
+#include <arm/nvidia/tegra_reg.h>
+#include <arm/nvidia/tegra_dcreg.h>
+#include <arm/nvidia/tegra_var.h>
+
+#define TEGRA_DC_NPORTS 2
+#define TEGRA_DC_DEPTH 32
+#define TEGRA_DC_FBALIGN 16
+
+static int tegra_dc_match(device_t, cfdata_t, void *);
+static void tegra_dc_attach(device_t, device_t, void *);
+
+struct tegra_dc_softc {
+ device_t sc_dev;
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