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[src/netbsd-7]: src Pull up following revision(s) (requested by msaitoh in ti...
details: https://anonhg.NetBSD.org/src/rev/2173eacc165e
branches: netbsd-7
changeset: 799288:2173eacc165e
user: snj <snj%NetBSD.org@localhost>
date: Sat May 09 08:35:10 2015 +0000
description:
Pull up following revision(s) (requested by msaitoh in ticket #739):
sys/arch/x86/include/specialreg.h: revision 1.82
usr.sbin/cpuctl/arch/i386.c: revision 1.66
>From Intel SDM:
- Add the Silicon Debug bit in CPUID Fn00000001 %ecx
- Add CPUID Fn0000_0007 %ecx bits
- Add comments.
--
Update some Intel CPU models (Sky Lake, Broadwell and Atom X[357]).
diffstat:
sys/arch/x86/include/specialreg.h | 32 +++++++++++++++++++++++++-------
usr.sbin/cpuctl/arch/i386.c | 12 +++++++-----
2 files changed, 32 insertions(+), 12 deletions(-)
diffs (123 lines):
diff -r 230155580da3 -r 2173eacc165e sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Thu May 07 20:42:48 2015 +0000
+++ b/sys/arch/x86/include/specialreg.h Sat May 09 08:35:10 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.78.4.2 2015/01/09 10:33:07 martin Exp $ */
+/* $NetBSD: specialreg.h,v 1.78.4.3 2015/05/09 08:35:10 snj Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -189,7 +189,7 @@
#define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */
#define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */
#define CPUID2_CID 0x00000400 /* Context ID */
-/* bit 11 unused 0x00000800 */
+#define CPUID2_SDBG 0x00000800 /* Silicon Debug */
#define CPUID2_FMA 0x00001000 /* has Fused Multiply Add */
#define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */
#define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */
@@ -214,7 +214,7 @@
#define CPUID2_FLAGS1 "\20" \
"\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \
"\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \
- "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "B11" \
+ "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "SDBG" \
"\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \
"\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \
"\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \
@@ -300,9 +300,14 @@
#define CPUID_DSPM_FLAGS1 "\20" "\1" "HWF" "\4" "EPB"
/*
- * Intel Structured Extended Feature leaf
- * Fn0000_0007 main leaf - %ebx.
+ * Intel Structured Extended Feature leaf Fn0000_0007
+ * %eax == 0: Subleaf 0
+ * %eax: The Maximun input value for supported subleaf.
+ * %ebx: Feature bits.
+ * %ecx: Feature bits.
*/
+
+/* %ebx */
#define CPUID_SEF_FSGSBASE __BIT(0)
#define CPUID_SEF_TSC_ADJUST __BIT(1)
#define CPUID_SEF_BMI1 __BIT(3)
@@ -337,17 +342,29 @@
"\32" "PT" "\33" "AVX512PF""\34" "AVX512ER"\
"\35" "AVX512CD""\36" "SHA"
+/* %ecx */
+#define CPUID_SEF_PREFETCHWT1 __BIT(0)
+#define CPUID_SEF_PKU __BIT(3)
+#define CPUID_SEF_OSPKE __BIT(4)
+
+#define CPUID_SEF_FLAGS1 "\20" \
+ "\1" "PREFETCHWT1" "\4" "PKU" \
+ "\5" "OSPKE"
+
/*
* CPUID Processor extended state Enumeration Fn0000000d
*
* %ecx == 0: supported features info:
* %eax: Valid bits of lower 32bits of XCR0
- * %ebx Save area size for features enabled in XCR0
- * %ecx Maximim save area size for all cpu features
+ * %ebx: Maximum save area size for features enabled in XCR0
+ * %ecx: Maximim save area size for all cpu features
* %edx: Valid bits of upper 32bits of XCR0
*
* %ecx == 1:
* %eax: Bit 0 => xsaveopt instruction avalaible (sandy bridge onwards)
+ * %ebx: Save area size for features enabled by XCR0 | IA32_XSS
+ * %ecx: Valid bits of lower 32bits of IA32_XSS
+ * %edx: Valid bits of upper 32bits of IA32_XSS
*
* %ecx >= 2: Save area details for XCR0 bit n
* %eax: size of save area for this feature
@@ -356,6 +373,7 @@
* All of %eax, %ebx, %ecx and %edx are zero for unsupported features.
*/
+/* %ecx=1 %eax */
#define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */
#define CPUID_PES1_XSAVEC 0x00000002 /* xsavec & compacted XRSTOR */
#define CPUID_PES1_XGETBV 0x00000004 /* xgetbv with ECX = 1 */
diff -r 230155580da3 -r 2173eacc165e usr.sbin/cpuctl/arch/i386.c
--- a/usr.sbin/cpuctl/arch/i386.c Thu May 07 20:42:48 2015 +0000
+++ b/usr.sbin/cpuctl/arch/i386.c Sat May 09 08:35:10 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.58.2.3 2015/04/19 16:42:19 riz Exp $ */
+/* $NetBSD: i386.c,v 1.58.2.4 2015/05/09 08:35:10 snj Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.58.2.3 2015/04/19 16:42:19 riz Exp $");
+__RCSID("$NetBSD: i386.c,v 1.58.2.4 2015/05/09 08:35:10 snj Exp $");
#endif /* not lint */
#include <sys/types.h>
@@ -363,15 +363,17 @@
"(Haswell)",
[0x46] = "4th gen Core, Xeon E3-12xx v3 "
"(Haswell)",
+ [0x47] = "5th gen Core (Broadwell)",
[0x4a] = "Atom Z3400",
- [0x4c] = "Atom Z8000",
+ [0x4c] = "Atom X[57]-Z8000 (Airmont)",
[0x4d] = "Atom C2000",
- [0x4e] = "Future gen Core",
+ [0x4e] = "Next gen Core (Sky Lake)",
[0x4f] = "Future gen Xeon (Broadwell)",
[0x56] = "Next gen Xeon D (Broadwell)",
[0x57] = "Next gen Xeon Phi",
[0x5a] = "Atom E3500",
- [0x5d] = "Future Atom (Silvermont)",
+ [0x5d] = "Atom X3-C3000 (Silvermont)",
+ [0x5e] = "Next gen Core (Sky Lake)",
},
"Pentium Pro, II or III", /* Default */
NULL,
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