[src/trunk]: src/sys/arch/arm Make PJ4B support code compilable.

[rkujawa <rkujawa%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/a43a76de9884
branches:  trunk
changeset: 786895:a43a76de9884
user:      rkujawa <rkujawa%NetBSD.org@localhost>
date:      Sun May 19 15:51:10 2013 +0000

description:
Make PJ4B support code compilable.

Obtained from Marvell, Semihalf.

diffstat:

 sys/arch/arm/conf/files.arm    |   7 ++++---
 sys/arch/arm/include/cpuconf.h |   9 +++++----
 sys/arch/arm/include/cpufunc.h |  31 +++++++++++++++++++++++++++++--
 3 files changed, 38 insertions(+), 9 deletions(-)

diffs (120 lines):

diff -r ce10e544aab1 -r a43a76de9884 sys/arch/arm/conf/files.arm
--- a/sys/arch/arm/conf/files.arm       Sun May 19 15:42:23 2013 +0000
+++ b/sys/arch/arm/conf/files.arm       Sun May 19 15:51:10 2013 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: files.arm,v 1.116 2013/02/14 07:26:23 matt Exp $
+#      $NetBSD: files.arm,v 1.117 2013/05/19 15:51:10 rkujawa Exp $
 
 # temporary define to allow easy moving to ../arch/arm/arm32
 defflag                                ARM32
@@ -8,7 +8,7 @@
 defflag        opt_cputypes.h          CPU_ARM6 CPU_ARM7 CPU_ARM7TDMI CPU_ARM8
                                CPU_ARM9 CPU_ARM9E CPU_ARM10 CPU_ARM11
                                CPU_SA110 CPU_SA1100 CPU_SA1110 CPU_IXP12X0
-                               CPU_FA526 CPU_CORTEX
+                               CPU_FA526 CPU_CORTEX CPU_PJ4B
                                CPU_XSCALE_80200 CPU_XSCALE_80321
                                CPU_XSCALE_PXA250 CPU_XSCALE_PXA270
                                CPU_XSCALE_IXP425 
@@ -136,7 +136,8 @@
 file   arch/arm/arm/cpufunc_asm_armv5_ec.S     cpu_arm9e | cpu_arm10 |
                                                        cpu_sheeva
 file   arch/arm/arm/cpufunc_asm_armv6.S        cpu_arm11 | cpu_cortex
-file   arch/arm/arm/cpufunc_asm_armv7.S        cpu_cortex
+file   arch/arm/arm/cpufunc_asm_armv7.S        cpu_cortex | cpu_pj4b
+file   arch/arm/arm/cpufunc_asm_pj4b.S         cpu_pj4b
 file   arch/arm/arm/cpufunc_asm_sa1.S          cpu_sa110 | cpu_sa1100 |
                                                        cpu_sa1110 |
                                                        cpu_ixp12x0
diff -r ce10e544aab1 -r a43a76de9884 sys/arch/arm/include/cpuconf.h
--- a/sys/arch/arm/include/cpuconf.h    Sun May 19 15:42:23 2013 +0000
+++ b/sys/arch/arm/include/cpuconf.h    Sun May 19 15:51:10 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpuconf.h,v 1.20 2011/03/10 07:47:14 bsh Exp $ */
+/*     $NetBSD: cpuconf.h,v 1.21 2013/05/19 15:51:10 rkujawa Exp $     */
 
 /*
  * Copyright (c) 2002 Wasabi Systems, Inc.
@@ -132,7 +132,7 @@
 #define ARM_ARCH_6     0
 #endif
 
-#if defined(CPU_CORTEX)
+#if defined(CPU_CORTEX) || defined(CPU_PJ4B)
 #define ARM_ARCH_7     1
 #else
 #define ARM_ARCH_7     0
@@ -217,7 +217,8 @@
        defined(CPU_ARM1136) || \
        defined(CPU_ARM1176) || \
        defined(CPU_ARM11) && \
-       !defined(CPU_CORTEX) && !defined(CPU_ARM11MPCORE)
+       !defined(CPU_CORTEX) && \
+       !defined(CPU_ARM11MPCORE) && !defined(CPU_PJ4B)
 #define        ARM_MMU_V6C             1
 #else
 #define        ARM_MMU_V6C             0
@@ -234,7 +235,7 @@
 
 
 #if !defined(_KERNEL_OPT) ||                                           \
-        defined(CPU_CORTEX)
+        defined(CPU_CORTEX) || defined(CPU_PJ4B)
 #define        ARM_MMU_V7              1
 #else
 #define        ARM_MMU_V7              0
diff -r ce10e544aab1 -r a43a76de9884 sys/arch/arm/include/cpufunc.h
--- a/sys/arch/arm/include/cpufunc.h    Sun May 19 15:42:23 2013 +0000
+++ b/sys/arch/arm/include/cpufunc.h    Sun May 19 15:51:10 2013 +0000
@@ -221,6 +221,8 @@
 u_int  cpufunc_faultstatus     (void);
 u_int  cpufunc_faultaddress    (void);
 
+u_int  cpu_pfr                 (int);
+
 #if defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)
 void   arm3_cache_flush        (void);
 #endif /* CPU_ARM2 || CPU_ARM250 || CPU_ARM3 */
@@ -468,8 +470,6 @@
 void   armv7_dcache_inv_range(vaddr_t, vsize_t);
 void   armv7_idcache_wbinv_range(vaddr_t, vsize_t);
 
-void   armv7_dcache_wbinv_all (void);
-void   armv7_idcache_wbinv_all(void);
 void   armv7_icache_sync_all(void);
 void   armv7_cpu_sleep(int);
 void   armv7_context_switch(u_int);
@@ -478,6 +478,33 @@
 void   armv7_setup(char *string);
 #endif
 
+#if defined(CPU_CORTEX) || defined(CPU_PJ4B)
+void   armv7_dcache_wbinv_all (void);
+void   armv7_idcache_wbinv_all(void);
+#endif
+
+#if defined(CPU_PJ4B)
+void   pj4b_setttb(u_int, bool);
+void   pj4b_tlb_flushID(void);
+void   pj4b_tlb_flushID_SE(u_int);
+
+void   pj4b_icache_sync_range(vm_offset_t, vm_size_t);
+void   pj4b_idcache_wbinv_range(vm_offset_t, vm_size_t);
+void   pj4b_dcache_wbinv_range(vm_offset_t, vm_size_t);
+void   pj4b_dcache_inv_range(vm_offset_t, vm_size_t);
+void   pj4b_dcache_wb_range(vm_offset_t, vm_size_t);
+
+void   pj4b_drain_writebuf(void);
+void   pj4b_drain_readbuf(void);
+void   pj4b_flush_brnchtgt_all(void);
+void   pj4b_flush_brnchtgt_va(u_int);
+void   pj4b_context_switch(u_int);
+void   pj4b_sleep(int);
+
+void   pj4bv7_setup(char *string);
+void   pj4b_config(void);
+
+#endif /* CPU_PJ4B */
 
 #if defined(CPU_ARM1136) || defined(CPU_ARM1176)
 void   arm11x6_setttb                  (u_int, bool);