[src/trunk]: src/sys/arch/x86/include Add a comment about APICBASE_PHYSADDR. ...

[maxv <maxv%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/d789aa09071c
branches:  trunk
changeset: 826017:d789aa09071c
user:      maxv <maxv%NetBSD.org@localhost>
date:      Fri Aug 11 06:27:12 2017 +0000

description:
Add a comment about APICBASE_PHYSADDR. Has to do with PR/42597.

diffstat:

 sys/arch/x86/include/specialreg.h |  7 ++++++-
 1 files changed, 6 insertions(+), 1 deletions(-)

diffs (21 lines):

diff -r 6188c7ba5315 -r d789aa09071c sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Fri Aug 11 06:18:29 2017 +0000
+++ b/sys/arch/x86/include/specialreg.h Fri Aug 11 06:27:12 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.100 2017/07/11 14:00:15 gson Exp $    */
+/*     $NetBSD: specialreg.h,v 1.101 2017/08/11 06:27:12 maxv Exp $    */
 
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
@@ -554,6 +554,11 @@
 #define        APICBASE_BSP            0x00000100      /* boot processor */
 #define        APICBASE_EXTD           0x00000400      /* x2APIC mode */
 #define        APICBASE_EN             0x00000800      /* software enable */
+/*
+ * APICBASE_PHYSADDR is actually variable-sized on some CPUs. But we're
+ * only interested in the initial value, which is guaranteed to fit the
+ * first 32 bits. So this macro is fine.
+ */
 #define        APICBASE_PHYSADDR       0xfffff000      /* physical address */
 #define MSR_EBL_CR_POWERON     0x02a
 #define MSR_EBC_FREQUENCY_ID   0x02c   /* PIV only */