[src/netbsd-7]: src Pull up following revision(s) (requested by msaitoh in ti...

[martin <martin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/0e9f4cb2a444
branches:  netbsd-7
changeset: 798692:0e9f4cb2a444
user:      martin <martin%NetBSD.org@localhost>
date:      Fri Dec 12 16:44:35 2014 +0000

description:
Pull up following revision(s) (requested by msaitoh in ticket #310):
        sys/arch/x86/include/specialreg.h: revision 1.79-1.80
        usr.sbin/cpuctl/arch/i386.c: revision 1.59
        sys/arch/x86/include/cacheinfo.h: revision 1.19

Update some cpuid related values:
- Add XSAVECC, XGETBV, XSAVES, SMAP and PQE
- Change XINUSE to XGETBV
- Add new cache descripter value (0xc3)
- Update signatures for the follwing CPUs:
  - Core M-5xxx
  - Core i7 Extreme
  - Future Core (0x4e)
  - Future Xeon (0x56)

diffstat:

 sys/arch/x86/include/cacheinfo.h  |   3 ++-
 sys/arch/x86/include/specialreg.h |  11 ++++++++---
 usr.sbin/cpuctl/arch/i386.c       |  14 +++++++++-----
 3 files changed, 19 insertions(+), 9 deletions(-)

diffs (106 lines):

diff -r 9e741d1800e8 -r 0e9f4cb2a444 sys/arch/x86/include/cacheinfo.h
--- a/sys/arch/x86/include/cacheinfo.h  Fri Dec 12 16:38:48 2014 +0000
+++ b/sys/arch/x86/include/cacheinfo.h  Fri Dec 12 16:44:35 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cacheinfo.h,v 1.18 2014/07/03 17:24:33 msaitoh Exp $   */
+/*     $NetBSD: cacheinfo.h,v 1.18.2.1 2014/12/12 16:44:35 martin Exp $        */
 
 #ifndef _X86_CACHEINFO_H_
 #define _X86_CACHEINFO_H_
@@ -247,6 +247,7 @@
 __CI_TBL(CAI_DTLB2,    0xc0,    4,  8,        4 * 1024, "4K/4M: 8 entries"), \
 __CI_TBL(CAI_L2_STLB2, 0xc1,    8,1024,       4 * 1024, "4K/2M: 1024 entries"), \
 __CI_TBL(CAI_DTLB2,    0xc2,    4, 16,        4 * 1024, "4K/2M: 16 entries"), \
+__CI_TBL(CAI_L2_STLB,  0xc3,    6,1536,       4 * 1024, NULL), \
 __CI_TBL(CAI_L2_STLB,  0xca,    4,512,        4 * 1024, NULL), \
 __CI_TBL(CAI_ICACHE,   0x06,    4,        8 * 1024, 32, NULL), \
 __CI_TBL(CAI_ICACHE,   0x08,    4,       16 * 1024, 32, NULL), \
diff -r 9e741d1800e8 -r 0e9f4cb2a444 sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Fri Dec 12 16:38:48 2014 +0000
+++ b/sys/arch/x86/include/specialreg.h Fri Dec 12 16:44:35 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.78 2014/02/25 22:11:11 dsl Exp $      */
+/*     $NetBSD: specialreg.h,v 1.78.4.1 2014/12/12 16:44:35 martin Exp $       */
 
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
@@ -87,6 +87,7 @@
 #define CR4_PCIDE      0x00020000 /* enable Process Context IDentifiers */
 #define CR4_OSXSAVE    0x00040000 /* enable xsave and xrestore */
 #define CR4_SMEP       0x00100000 /* enable SMEP support */
+#define CR4_SMAP       0x00200000 /* enable SMAP support */
 
 /*
  * Extended Control Register XCR0
@@ -315,6 +316,7 @@
 #define CPUID_SEF_QM           __BIT(12)
 #define CPUID_SEF_FPUCSDS      __BIT(13)
 #define CPUID_SEF_MPX          __BIT(14)
+#define CPUID_SEF_PQE          __BIT(15)
 #define CPUID_SEF_AVX512F      __BIT(16)
 #define CPUID_SEF_RDSEED       __BIT(18)
 #define CPUID_SEF_ADX          __BIT(19)
@@ -329,7 +331,7 @@
        "\1" "FSGSBASE" "\2" "TSCADJUST"                "\4" "BMI1"     \
        "\5" "HLE"      "\6" "AVX2"                     "\10" "SMEP"    \
        "\11" "BMI2"    "\12" "ERMS"    "\13" "INVPCID" "\14" "RTM"     \
-       "\15" "QM"      "\16" "FPUCSDS" "\17" "MPX"                     \
+       "\15" "QM"      "\16" "FPUCSDS" "\17" "MPX"     "\20" "PQE"     \
        "\21" "AVX512F"                 "\23" "RDSEED"  "\24" "ADX"     \
        "\25" "SMAP"                                                    \
                        "\32" "PT"      "\33" "AVX512PF""\34" "AVX512ER"\
@@ -355,9 +357,12 @@
  */
 
 #define        CPUID_PES1_XSAVEOPT     0x00000001      /* xsaveopt instruction */
+#define        CPUID_PES1_XSAVEC       0x00000002      /* xsavec & compacted XRSTOR */
+#define        CPUID_PES1_XGETBV       0x00000004      /* xgetbv with ECX = 1 */
+#define        CPUID_PES1_XSAVES       0x00000008      /* xsaves/xrstors, IA32_XSS */
 
 #define CPUID_PES1_FLAGS       "\20" \
-       "\1" "XSAVEOPT"
+       "\1" "XSAVEOPT" "\2" "XSAVEC"   "\3" "XGETBV"   "\4" "XSAVES"
 
 /* Intel Fn80000001 extended features - %edx */
 #define CPUID_SYSCALL  0x00000800      /* SYSCALL/SYSRET */
diff -r 9e741d1800e8 -r 0e9f4cb2a444 usr.sbin/cpuctl/arch/i386.c
--- a/usr.sbin/cpuctl/arch/i386.c       Fri Dec 12 16:38:48 2014 +0000
+++ b/usr.sbin/cpuctl/arch/i386.c       Fri Dec 12 16:44:35 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: i386.c,v 1.58 2014/07/25 14:18:49 msaitoh Exp $        */
+/*     $NetBSD: i386.c,v 1.58.2.1 2014/12/12 16:44:35 martin Exp $     */
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include <sys/cdefs.h>
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.58 2014/07/25 14:18:49 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.58.2.1 2014/12/12 16:44:35 martin Exp $");
 #endif /* not lint */
 
 #include <sys/types.h>
@@ -353,15 +353,19 @@
                                         "Ivy Bridge",
                                [0x3c] = "4th gen Core, Xeon E3-12xx v3 "
                                         "(Haswell)",
-                               [0x3d] = "Core M based on Broadwell",
-                               [0x3e] = "Xeon E5/E7, Ivy Bridge-EP",
-                               [0x3f] = "Next gen Xeon based on Haswell",
+                               [0x3d] = "Core M-5xxx (Broadwell)",
+                               [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), "
+                                        "Core i7-49xx Extreme",
+                               [0x3f] = "Xeon E5-2600/1600 v3 (Haswell-E), "
+                                        "Core i7-59xx Extreme",
                                [0x45] = "4th gen Core, Xeon E3-12xx v3 "
                                         "(Haswell)",
                                [0x46] = "4th gen Core, Xeon E3-12xx v3 "
                                         "(Haswell)",
                                [0x4a] = "Future Atom E3000, Z3000",
                                [0x4d] = "Atom C2000",
+                               [0x4e] = "Future Core",
+                               [0x56] = "Future Xeon",
                                [0x5a] = "Future Atom E3000, Z3000",
                                [0x5d] = "Future Atom E3000, Z3000",
                        },