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[src/trunk]: src/sys/arch/arm/sunxi Disable poorly implemented tx interrupt m...
details: https://anonhg.NetBSD.org/src/rev/69cdaf552cb6
branches: trunk
changeset: 826829:69cdaf552cb6
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sun Oct 01 15:05:09 2017 +0000
description:
Disable poorly implemented tx interrupt mitigation code, fix checksum
offload support.
diffstat:
sys/arch/arm/sunxi/sunxi_emac.c | 21 +++++++--------------
sys/arch/arm/sunxi/sunxi_emac.h | 34 ++++++++++++++++++++++++++++++----
2 files changed, 37 insertions(+), 18 deletions(-)
diffs (159 lines):
diff -r 4e84963e10ce -r 69cdaf552cb6 sys/arch/arm/sunxi/sunxi_emac.c
--- a/sys/arch/arm/sunxi/sunxi_emac.c Sun Oct 01 10:45:49 2017 +0000
+++ b/sys/arch/arm/sunxi/sunxi_emac.c Sun Oct 01 15:05:09 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_emac.c,v 1.7 2017/09/19 17:26:45 jmcneill Exp $ */
+/* $NetBSD: sunxi_emac.c,v 1.8 2017/10/01 15:05:09 jmcneill Exp $ */
/*-
* Copyright (c) 2016-2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -33,7 +33,7 @@
#include "opt_net_mpsafe.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_emac.c,v 1.7 2017/09/19 17:26:45 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_emac.c,v 1.8 2017/10/01 15:05:09 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -95,7 +95,6 @@
#define BURST_LEN_DEFAULT 8
#define RX_TX_PRI_DEFAULT 0
#define PAUSE_TIME_DEFAULT 0x400
-#define TX_INTERVAL_DEFAULT 64
/* syscon EMAC clock register */
#define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */
@@ -125,9 +124,6 @@
/* Pause time field in the transmitted control frame */
static int sunxi_emac_pause_time = PAUSE_TIME_DEFAULT;
-/* Request a TX interrupt every <n> descriptors */
-static int sunxi_emac_tx_interval = TX_INTERVAL_DEFAULT;
-
enum sunxi_emac_type {
EMAC_A83T = 1,
EMAC_H3,
@@ -337,8 +333,6 @@
} else {
status = TX_DESC_CTL;
size = flags | len;
- if ((index & (sunxi_emac_tx_interval - 1)) == 0)
- size |= TX_INT_CTL;
++sc->tx.queued;
}
@@ -380,7 +374,7 @@
for (cur = index, i = 0; i < nsegs; i++) {
sc->tx.buf_map[cur].mbuf = (i == 0 ? m : NULL);
if (i == nsegs - 1)
- flags |= TX_LAST_DESC;
+ flags |= TX_LAST_DESC | TX_INT_CTL;
sunxi_emac_setup_txdesc(sc, cur, flags, segs[i].ds_addr,
segs[i].ds_len);
@@ -740,15 +734,14 @@
if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0 &&
(status & RX_FRM_TYPE) != 0) {
- m->m_pkthdr.csum_flags = M_CSUM_IPv4;
+ m->m_pkthdr.csum_flags = M_CSUM_IPv4 |
+ M_CSUM_TCPv4 | M_CSUM_UDPv4;
if ((status & RX_HEADER_ERR) != 0)
m->m_pkthdr.csum_flags |=
M_CSUM_IPv4_BAD;
- if ((status & RX_PAYLOAD_ERR) == 0) {
+ if ((status & RX_PAYLOAD_ERR) != 0)
m->m_pkthdr.csum_flags |=
- M_CSUM_DATA;
- m->m_pkthdr.csum_data = 0xffff;
- }
+ M_CSUM_TCP_UDP_BAD;
}
++npkt;
diff -r 4e84963e10ce -r 69cdaf552cb6 sys/arch/arm/sunxi/sunxi_emac.h
--- a/sys/arch/arm/sunxi/sunxi_emac.h Sun Oct 01 10:45:49 2017 +0000
+++ b/sys/arch/arm/sunxi/sunxi_emac.h Sun Oct 01 15:05:09 2017 +0000
@@ -47,24 +47,39 @@
#define BASIC_CTL_RX_TX_PRI (1 << 1)
#define BASIC_CTL_SOFT_RST (1 << 0)
#define EMAC_INT_STA 0x08
-#define RX_BUF_UA_INT (1 << 10)
+#define RGMII_LINK_STA_INT (1 << 16)
+#define RX_EARLY_INT (1 << 13)
+#define RX_OVERFLOW_INT (1 << 12)
+#define RX_TIMEOUT_INT (1 << 11)
+#define RX_DMA_STOPPED_INT (1 << 10)
+#define RX_BUF_UA_INT (1 << 9)
#define RX_INT (1 << 8)
+#define TX_EARLY_INT (1 << 5)
#define TX_UNDERFLOW_INT (1 << 4)
+#define TX_TIMEOUT_INT (1 << 3)
#define TX_BUF_UA_INT (1 << 2)
#define TX_DMA_STOPPED_INT (1 << 1)
#define TX_INT (1 << 0)
#define EMAC_INT_EN 0x0c
-#define RX_BUF_UA_INT_EN (1 << 10)
+#define RX_EARLY_INT_EN (1 << 13)
+#define RX_OVERFLOW_INT_EN (1 << 12)
+#define RX_TIMEOUT_INT_EN (1 << 11)
+#define RX_DMA_STOPPED_INT_EN (1 << 10)
+#define RX_BUF_UA_INT_EN (1 << 9)
#define RX_INT_EN (1 << 8)
+#define TX_EARLY_INT_EN (1 << 5)
#define TX_UNDERFLOW_INT_EN (1 << 4)
+#define TX_TIMEOUT_INT_EN (1 << 3)
#define TX_BUF_UA_INT_EN (1 << 2)
#define TX_DMA_STOPPED_INT_EN (1 << 1)
#define TX_INT_EN (1 << 0)
#define EMAC_TX_CTL_0 0x10
#define TX_EN (1 << 31)
+#define TX_FRM_LEN_CTL (1 << 30)
#define EMAC_TX_CTL_1 0x14
#define TX_DMA_START (1 << 31)
#define TX_DMA_EN (1 << 30)
+#define TX_TH (0x7 << 8)
#define TX_NEXT_FRAME (1 << 2)
#define TX_MD (1 << 1)
#define FLUSH_TX_FIFO (1 << 0)
@@ -75,14 +90,23 @@
#define EMAC_TX_DMA_LIST 0x20
#define EMAC_RX_CTL_0 0x24
#define RX_EN (1 << 31)
+#define RX_FRM_LEN_CTL (1 << 30)
#define JUMBO_FRM_EN (1 << 29)
#define STRIP_FCS (1 << 28)
#define CHECK_CRC (1 << 27)
+#define RX_PAUSE_FRM_MD (1 << 17)
#define RX_FLOW_CTL_EN (1 << 16)
#define EMAC_RX_CTL_1 0x28
#define RX_DMA_START (1 << 31)
#define RX_DMA_EN (1 << 30)
+#define RX_FIFO_FLOW_CTL (1 << 24)
+#define RX_FLOW_CTL_TH_DEACT (0x3 << 22)
+#define RX_FLOW_CTL_TH_ACT (0x3 << 20)
+#define RX_TH (0x3 << 4)
+#define RX_ERR_FRM (1 << 3)
+#define RX_RUNT_FRM (1 << 2)
#define RX_MD (1 << 1)
+#define FLUSH_RX_FRM (1 << 0)
#define EMAC_RX_DMA_LIST 0x34
#define EMAC_RX_FRM_FLT 0x38
#define DIS_ADDR_FILTER (1 << 31)
@@ -167,11 +191,13 @@
#define TX_CHECKSUM_CTL_FULL 3
#define TX_CHECKSUM_CTL_SHIFT 27
#define TX_CRC_CTL (1 << 26)
-#define TX_BUF_SIZE (0xfff << 0)
+#define TX_CHAIN_DESC (1 << 24)
+#define TX_BUF_SIZE (0x7ff << 0)
#define TX_BUF_SIZE_SHIFT 0
/* Receive */
#define RX_INT_CTL (1 << 31)
-#define RX_BUF_SIZE (0xfff << 0)
+#define RX_CHAIN_DESC (1 << 24)
+#define RX_BUF_SIZE (0x7ff << 0)
#define RX_BUF_SIZE_SHIFT 0
uint32_t addr;
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