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[src/trunk]: src/sys/arch/arm/sunxi Add Allwinner A80 (sun9i) support.
details: https://anonhg.NetBSD.org/src/rev/ebe484d37dd9
branches: trunk
changeset: 827010:ebe484d37dd9
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sun Oct 08 18:00:36 2017 +0000
description:
Add Allwinner A80 (sun9i) support.
diffstat:
sys/arch/arm/sunxi/files.sunxi | 15 +-
sys/arch/arm/sunxi/sun9i_a80_ccu.c | 325 ++++++++++++++++++++++++++++++++++
sys/arch/arm/sunxi/sun9i_a80_ccu.h | 215 ++++++++++++++++++++++
sys/arch/arm/sunxi/sun9i_a80_gpio.c | 221 +++++++++++++++++++++++
sys/arch/arm/sunxi/sun9i_a80_mmcclk.c | 100 ++++++++++
sys/arch/arm/sunxi/sunxi_gpio.c | 81 +++++---
sys/arch/arm/sunxi/sunxi_gpio.h | 8 +-
sys/arch/arm/sunxi/sunxi_mmc.c | 24 ++-
sys/arch/arm/sunxi/sunxi_platform.c | 36 +++-
sys/arch/arm/sunxi/sunxi_platform.h | 4 +-
10 files changed, 990 insertions(+), 39 deletions(-)
diffs (truncated from 1293 to 300 lines):
diff -r e4a0e638f4af -r ebe484d37dd9 sys/arch/arm/sunxi/files.sunxi
--- a/sys/arch/arm/sunxi/files.sunxi Sun Oct 08 15:29:33 2017 +0000
+++ b/sys/arch/arm/sunxi/files.sunxi Sun Oct 08 18:00:36 2017 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.sunxi,v 1.31 2017/10/07 21:53:16 jmcneill Exp $
+# $NetBSD: files.sunxi,v 1.32 2017/10/08 18:00:36 jmcneill Exp $
#
# Configuration info for Allwinner sunxi family SoCs
#
@@ -58,6 +58,11 @@
attach sun8ih3rccu at fdt with sunxi_h3_r_ccu
file arch/arm/sunxi/sun8i_h3_r_ccu.c sunxi_h3_r_ccu
+# CCU (A80)
+device sun9ia80ccu: sunxi_ccu
+attach sun9ia80ccu at fdt with sunxi_a80_ccu
+file arch/arm/sunxi/sun9i_a80_ccu.c sunxi_a80_ccu
+
# CCU (A64)
device sun50ia64ccu: sunxi_ccu
attach sun50ia64ccu at fdt with sunxi_a64_ccu
@@ -78,6 +83,11 @@
attach sunxigmacclk at fdt with sunxi_gmacclk
file arch/arm/sunxi/sunxi_gmacclk.c sunxi_gmacclk
+# SD/MMC-COMM (A80)
+device sun9immcclk
+attach sun9immcclk at fdt with sunxi_a80_mmcclk
+file arch/arm/sunxi/sun9i_a80_mmcclk.c sunxi_a80_mmcclk
+
# Interrupt controller
device sunxiintc: pic, pic_splfuncs
attach sunxiintc at fdt with sunxi_intc
@@ -93,6 +103,7 @@
file arch/arm/sunxi/sun7i_a20_gpio.c sunxi_gpio & soc_sun7i_a20
file arch/arm/sunxi/sun8i_a83t_gpio.c sunxi_gpio & soc_sun8i_a83t
file arch/arm/sunxi/sun8i_h3_gpio.c sunxi_gpio & soc_sun8i_h3
+file arch/arm/sunxi/sun9i_a80_gpio.c sunxi_gpio & soc_sun9i_a80
file arch/arm/sunxi/sun50i_a64_gpio.c sunxi_gpio & soc_sun50i_a64
# UART
@@ -213,5 +224,7 @@
defflag opt_soc.h SOC_SUN8I: SOC_SUNXI
defflag opt_soc.h SOC_SUN8I_A83T: SOC_SUN8I
defflag opt_soc.h SOC_SUN8I_H3: SOC_SUN8I
+defflag opt_soc.h SOC_SUN9I: SOC_SUNXI
+defflag opt_soc.h SOC_SUN9I_A80: SOC_SUN9I
defflag opt_soc.h SOC_SUN50I: SOC_SUNXI
defflag opt_soc.h SOC_SUN50I_A64: SOC_SUN50I
diff -r e4a0e638f4af -r ebe484d37dd9 sys/arch/arm/sunxi/sun9i_a80_ccu.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/sunxi/sun9i_a80_ccu.c Sun Oct 08 18:00:36 2017 +0000
@@ -0,0 +1,325 @@
+/* $NetBSD: sun9i_a80_ccu.c,v 1.1 2017/10/08 18:00:36 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: sun9i_a80_ccu.c,v 1.1 2017/10/08 18:00:36 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/sunxi/sunxi_ccu.h>
+#include <arm/sunxi/sun9i_a80_ccu.h>
+
+/* CCU */
+#define PLL_PERIPH0_CTRL_REG 0x00c
+#define PLL_PERIPH1_CTRL_REG 0x02c
+#define GTBUS_CLK_CFG_REG 0x05c
+#define AHB0_CLK_CFG_REG 0x060
+#define AHB1_CLK_CFG_REG 0x064
+#define AHB2_CLK_CFG_REG 0x068
+#define APB0_CLK_CFG_REG 0x070
+#define APB1_CLK_CFG_REG 0x074
+
+/* CCU_SCLK */
+#define SDMMC0_CLK_REG 0x410
+#define SDMMC1_CLK_REG 0x414
+#define SDMMC2_CLK_REG 0x418
+#define BUS_CLK_GATING_REG0 0x580
+#define BUS_CLK_GATING_REG1 0x584
+#define BUS_CLK_GATING_REG2 0x588
+#define BUS_CLK_GATING_REG3 0x590
+#define BUS_CLK_GATING_REG4 0x594
+#define BUS_SOFT_RST_REG0 0x5a0
+#define BUS_SOFT_RST_REG1 0x5a4
+#define BUS_SOFT_RST_REG2 0x5a8
+#define BUS_SOFT_RST_REG3 0x5b0
+#define BUS_SOFT_RST_REG4 0x5b4
+
+static int sun9i_a80_ccu_match(device_t, cfdata_t, void *);
+static void sun9i_a80_ccu_attach(device_t, device_t, void *);
+
+static const char * compatible[] = {
+ "allwinner,sun9i-a80-ccu",
+ NULL
+};
+
+CFATTACH_DECL_NEW(sunxi_a80_ccu, sizeof(struct sunxi_ccu_softc),
+ sun9i_a80_ccu_match, sun9i_a80_ccu_attach, NULL, NULL);
+
+static struct sunxi_ccu_reset sun9i_a80_ccu_resets[] = {
+ SUNXI_CCU_RESET(A80_RST_BUS_FD, BUS_SOFT_RST_REG0, 0),
+ SUNXI_CCU_RESET(A80_RST_BUS_GPU_CTRL, BUS_SOFT_RST_REG0, 3),
+ SUNXI_CCU_RESET(A80_RST_BUS_SS, BUS_SOFT_RST_REG0, 5),
+ SUNXI_CCU_RESET(A80_RST_BUS_MMC, BUS_SOFT_RST_REG0, 8),
+ SUNXI_CCU_RESET(A80_RST_BUS_NAND1, BUS_SOFT_RST_REG0, 12),
+ SUNXI_CCU_RESET(A80_RST_BUS_NAND0, BUS_SOFT_RST_REG0, 13),
+ SUNXI_CCU_RESET(A80_RST_BUS_TS, BUS_SOFT_RST_REG0, 18),
+ SUNXI_CCU_RESET(A80_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20),
+ SUNXI_CCU_RESET(A80_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21),
+ SUNXI_CCU_RESET(A80_RST_BUS_SPI2, BUS_SOFT_RST_REG0, 22),
+ SUNXI_CCU_RESET(A80_RST_BUS_SPI3, BUS_SOFT_RST_REG0, 23),
+
+ SUNXI_CCU_RESET(A80_RST_BUS_OTG_PHY, BUS_SOFT_RST_REG1, 1),
+ SUNXI_CCU_RESET(A80_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21),
+ SUNXI_CCU_RESET(A80_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22),
+ SUNXI_CCU_RESET(A80_RST_BUS_HSTIMER, BUS_SOFT_RST_REG1, 23),
+ SUNXI_CCU_RESET(A80_RST_BUS_DMA, BUS_SOFT_RST_REG1, 24),
+
+ SUNXI_CCU_RESET(A80_RST_BUS_LCD0, BUS_SOFT_RST_REG2, 0),
+ SUNXI_CCU_RESET(A80_RST_BUS_LCD1, BUS_SOFT_RST_REG2, 1),
+ SUNXI_CCU_RESET(A80_RST_BUS_CSI, BUS_SOFT_RST_REG2, 4),
+ SUNXI_CCU_RESET(A80_RST_BUS_DE, BUS_SOFT_RST_REG2, 7),
+ SUNXI_CCU_RESET(A80_RST_BUS_MP, BUS_SOFT_RST_REG2, 8),
+ SUNXI_CCU_RESET(A80_RST_BUS_GPU, BUS_SOFT_RST_REG2, 9),
+
+ SUNXI_CCU_RESET(A80_RST_BUS_LRADC, BUS_SOFT_RST_REG3, 15),
+ SUNXI_CCU_RESET(A80_RST_BUS_GPADC, BUS_SOFT_RST_REG3, 17),
+
+ SUNXI_CCU_RESET(A80_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0),
+ SUNXI_CCU_RESET(A80_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1),
+ SUNXI_CCU_RESET(A80_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2),
+ SUNXI_CCU_RESET(A80_RST_BUS_I2C3, BUS_SOFT_RST_REG4, 3),
+ SUNXI_CCU_RESET(A80_RST_BUS_I2C4, BUS_SOFT_RST_REG4, 4),
+ SUNXI_CCU_RESET(A80_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16),
+ SUNXI_CCU_RESET(A80_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17),
+ SUNXI_CCU_RESET(A80_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18),
+ SUNXI_CCU_RESET(A80_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19),
+ SUNXI_CCU_RESET(A80_RST_BUS_UART4, BUS_SOFT_RST_REG4, 20),
+ SUNXI_CCU_RESET(A80_RST_BUS_UART5, BUS_SOFT_RST_REG4, 21),
+};
+
+static const char *gtbus_parents[] = { "hosc", "pll_periph0", "pll_periph1" };
+static const char *ahb0_parents[] = { "gtbus", "pll_periph0", "pll_periph1" };
+static const char *ahb1_parents[] = { "gtbus", "pll_periph0", "pll_periph1" };
+static const char *ahb2_parents[] = { "hosc", "pll_periph0", "pll_periph1" };
+static const char *apb_parents[] = { "hosc", "pll_periph0" };
+static const char *mmc_parents[] = { "hosc", "pll_periph0" };
+
+static struct sunxi_ccu_clk sun9i_a80_ccu_clks[] = {
+ SUNXI_CCU_NKMP(A80_CLK_PLL_PERIPH0, "pll_periph0", "hosc",
+ PLL_PERIPH0_CTRL_REG, /* reg */
+ __BITS(15,8), /* n */
+ __BIT(16), /* k */
+ 0, /* m */
+ __BIT(18), /* p */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NKMP_FACTOR_N_EXACT),
+ SUNXI_CCU_NKMP(A80_CLK_PLL_PERIPH1, "pll_periph1", "hosc",
+ PLL_PERIPH1_CTRL_REG, /* reg */
+ __BITS(15,8), /* n */
+ __BIT(16), /* k */
+ 0, /* m */
+ __BIT(18), /* p */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NKMP_FACTOR_N_EXACT),
+
+ SUNXI_CCU_DIV(A80_CLK_GTBUS, "gtbus", gtbus_parents,
+ GTBUS_CLK_CFG_REG, /* reg */
+ __BITS(1,0), /* div */
+ __BITS(25,24), /* sel */
+ 0),
+
+ SUNXI_CCU_DIV(A80_CLK_AHB0, "ahb0", ahb0_parents,
+ AHB0_CLK_CFG_REG, /* reg */
+ __BITS(1,0), /* div */
+ __BITS(25,24), /* sel */
+ SUNXI_CCU_DIV_POWER_OF_TWO),
+
+ SUNXI_CCU_DIV(A80_CLK_AHB1, "ahb1", ahb1_parents,
+ AHB1_CLK_CFG_REG, /* reg */
+ __BITS(1,0), /* div */
+ __BITS(25,24), /* sel */
+ SUNXI_CCU_DIV_POWER_OF_TWO),
+
+ SUNXI_CCU_DIV(A80_CLK_AHB2, "ahb2", ahb2_parents,
+ AHB2_CLK_CFG_REG, /* reg */
+ __BITS(1,0), /* div */
+ __BITS(25,24), /* sel */
+ SUNXI_CCU_DIV_POWER_OF_TWO),
+
+ SUNXI_CCU_DIV(A80_CLK_APB0, "apb0", apb_parents,
+ APB0_CLK_CFG_REG, /* reg */
+ __BITS(1,0), /* div */
+ __BIT(24), /* sel */
+ SUNXI_CCU_DIV_POWER_OF_TWO),
+
+ SUNXI_CCU_NM(A80_CLK_APB1, "apb1", apb_parents,
+ APB1_CLK_CFG_REG, /* reg */
+ __BITS(17,16), /* n */
+ __BITS(4,0), /* m */
+ __BIT(24), /* sel */
+ 0, /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO),
+
+ SUNXI_CCU_NM(A80_CLK_MMC0, "mmc0", mmc_parents,
+ SDMMC0_CLK_REG, /* reg */
+ __BITS(17,16), /* n */
+ __BITS(3,0), /* m */
+ __BITS(27,24), /* sel */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO),
+ SUNXI_CCU_PHASE(A80_CLK_MMC0_SAMPLE, "mmc0_sample", "mmc0",
+ SDMMC0_CLK_REG, __BITS(22,20)),
+ SUNXI_CCU_PHASE(A80_CLK_MMC0_OUTPUT, "mmc0_output", "mmc0",
+ SDMMC0_CLK_REG, __BITS(10,8)),
+ SUNXI_CCU_NM(A80_CLK_MMC1, "mmc1", mmc_parents,
+ SDMMC1_CLK_REG, /* reg */
+ __BITS(17,16), /* n */
+ __BITS(3,0), /* m */
+ __BITS(27,24), /* sel */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO),
+ SUNXI_CCU_PHASE(A80_CLK_MMC1_SAMPLE, "mmc1_sample", "mmc1",
+ SDMMC1_CLK_REG, __BITS(22,20)),
+ SUNXI_CCU_PHASE(A80_CLK_MMC1_OUTPUT, "mmc1_output", "mmc1",
+ SDMMC1_CLK_REG, __BITS(10,8)),
+ SUNXI_CCU_NM(A80_CLK_MMC2, "mmc2", mmc_parents,
+ SDMMC2_CLK_REG, /* reg */
+ __BITS(17,16), /* n */
+ __BITS(3,0), /* m */
+ __BITS(27,24), /* sel */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO),
+ SUNXI_CCU_PHASE(A80_CLK_MMC2_SAMPLE, "mmc2_sample", "mmc2",
+ SDMMC2_CLK_REG, __BITS(22,20)),
+ SUNXI_CCU_PHASE(A80_CLK_MMC2_OUTPUT, "mmc2_output", "mmc2",
+ SDMMC2_CLK_REG, __BITS(10,8)),
+
+ SUNXI_CCU_GATE(A80_CLK_BUS_FD, "ahb0-fd", "ahb0",
+ BUS_CLK_GATING_REG0, 0),
+ SUNXI_CCU_GATE(A80_CLK_BUS_GPU_CTRL, "ahb0-gpu-ctrl", "ahb0",
+ BUS_CLK_GATING_REG0, 3),
+ SUNXI_CCU_GATE(A80_CLK_BUS_SS, "ahb0-ss", "ahb0",
+ BUS_CLK_GATING_REG0, 5),
+ SUNXI_CCU_GATE(A80_CLK_BUS_MMC, "ahb0-mmc", "ahb0",
+ BUS_CLK_GATING_REG0, 8),
+ SUNXI_CCU_GATE(A80_CLK_BUS_NAND1, "ahb0-nand1", "ahb0",
+ BUS_CLK_GATING_REG0, 12),
+ SUNXI_CCU_GATE(A80_CLK_BUS_NAND0, "ahb0-nand0", "ahb0",
+ BUS_CLK_GATING_REG0, 13),
+ SUNXI_CCU_GATE(A80_CLK_BUS_TS, "ahb0-ts", "ahb0",
+ BUS_CLK_GATING_REG0, 18),
+ SUNXI_CCU_GATE(A80_CLK_BUS_SPI0, "ahb0-spi0", "ahb0",
+ BUS_CLK_GATING_REG0, 20),
+ SUNXI_CCU_GATE(A80_CLK_BUS_SPI1, "ahb0-spi1", "ahb0",
+ BUS_CLK_GATING_REG0, 21),
+ SUNXI_CCU_GATE(A80_CLK_BUS_SPI2, "ahb0-spi2", "ahb0",
+ BUS_CLK_GATING_REG0, 22),
+ SUNXI_CCU_GATE(A80_CLK_BUS_SPI3, "ahb0-spi3", "ahb0",
+ BUS_CLK_GATING_REG0, 23),
+
+ SUNXI_CCU_GATE(A80_CLK_BUS_USB, "ahb1-usb", "ahb1",
+ BUS_CLK_GATING_REG1, 1),
+ SUNXI_CCU_GATE(A80_CLK_BUS_MSGBOX, "ahb1-msgbox", "ahb1",
+ BUS_CLK_GATING_REG1, 21),
+ SUNXI_CCU_GATE(A80_CLK_BUS_SPINLOCK, "ahb1-spinlock", "ahb1",
+ BUS_CLK_GATING_REG1, 22),
+ SUNXI_CCU_GATE(A80_CLK_BUS_HSTIMER, "ahb1-hstimer", "ahb1",
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