[src/trunk]: src/sys/arch/mips/mips Improve comments after some discussion wi...

[dholland <dholland%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/1eba67b30c35
branches:  trunk
changeset: 816421:1eba67b30c35
user:      dholland <dholland%NetBSD.org@localhost>
date:      Mon Jul 04 15:47:04 2016 +0000

description:
Improve comments after some discussion with Nick.

diffstat:

 sys/arch/mips/mips/locore_mips1.S |  11 ++++++++---
 sys/arch/mips/mips/mipsX_subr.S   |   8 ++++++--
 2 files changed, 14 insertions(+), 5 deletions(-)

diffs (47 lines):

diff -r b39c8bd6f195 -r 1eba67b30c35 sys/arch/mips/mips/locore_mips1.S
--- a/sys/arch/mips/mips/locore_mips1.S Mon Jul 04 15:45:37 2016 +0000
+++ b/sys/arch/mips/mips/locore_mips1.S Mon Jul 04 15:47:04 2016 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore_mips1.S,v 1.85 2015/06/11 07:30:10 matt Exp $   */
+/*     $NetBSD: locore_mips1.S,v 1.86 2016/07/04 15:47:04 dholland Exp $       */
 
 /*
  * Copyright (c) 1992, 1993
@@ -771,8 +771,13 @@
        move    s0, v0                          # remember previous priority
 
        /*
-        * Now that we are at IPL_HIGH, we can turn off FPU and turn on
-        * interrupts since they all masked.
+        * Now that we're at splhigh so all interrupts are masked
+        * individually and we won't get interrupted here, turn the
+        * global interrupt enable bit on again. This will allow
+        * high-priority interrupts to be delivered once a
+        * low-priority interrupt handler lowers spl to execute.
+        *
+        * Also switch off the FPU.
         */
        mfc0    v1, MIPS_COP_0_STATUS
 #ifndef NOFPU
diff -r b39c8bd6f195 -r 1eba67b30c35 sys/arch/mips/mips/mipsX_subr.S
--- a/sys/arch/mips/mips/mipsX_subr.S   Mon Jul 04 15:45:37 2016 +0000
+++ b/sys/arch/mips/mips/mipsX_subr.S   Mon Jul 04 15:47:04 2016 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mipsX_subr.S,v 1.65 2016/07/04 14:47:39 dholland Exp $ */
+/*     $NetBSD: mipsX_subr.S,v 1.66 2016/07/04 15:47:04 dholland Exp $ */
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -1083,7 +1083,11 @@
        INT_S   t1, CPU_INFO_IDEPTH(s2)         #   store new interrupt depth
 
        /*
-        * Now we can clear exception level since no interrupts can be delivered
+        * Now that we're at splhigh so all interrupts are masked
+        * individually and we won't get interrupted here, clear the
+        * exception level bit. This will allow high-priority
+        * interrupts to be delivered once a low-priority interrupt
+        * handler lowers spl to execute.
         */
        mfc0    v1, MIPS_COP_0_STATUS
        MFC0_HAZARD