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[src/trunk]: src/sys/arch/arm/imx Add support i.MX50x
details: https://anonhg.NetBSD.org/src/rev/f5d0618a4a1d
branches: trunk
changeset: 797661:f5d0618a4a1d
user: hkenken <hkenken%NetBSD.org@localhost>
date: Fri Jul 25 07:49:56 2014 +0000
description:
Add support i.MX50x
* i.MX50 series is e-ink e-reader processor.
diffstat:
sys/arch/arm/imx/files.imx51 | 12 +-
sys/arch/arm/imx/imx50_iomuxreg.h | 563 ++++++++++++++++++++++++++++++++++++++
sys/arch/arm/imx/imx51_ccm.c | 268 ++++++++++++++++-
sys/arch/arm/imx/imx51_ccmreg.h | 185 ++++++++----
sys/arch/arm/imx/imx51_ccmvar.h | 15 +-
sys/arch/arm/imx/imx51_clock.c | 8 +-
sys/arch/arm/imx/imx51_dpllreg.h | 17 +-
sys/arch/arm/imx/imx51_gpio.c | 10 +-
sys/arch/arm/imx/imx51_iomuxreg.h | 16 -
sys/arch/arm/imx/imx51_tzic.c | 5 +-
sys/arch/arm/imx/imx51_uart.c | 6 +-
sys/arch/arm/imx/imx51_usb.c | 18 +-
sys/arch/arm/imx/imx51reg.h | 303 +++++++++++---------
sys/arch/arm/imx/imxclock.c | 53 +-
sys/arch/arm/imx/imxsdmareg.h | 12 +-
sys/arch/arm/imx/imxusb.c | 53 ++-
sys/arch/arm/imx/imxusbreg.h | 48 +-
sys/arch/arm/imx/imxusbvar.h | 3 +-
18 files changed, 1253 insertions(+), 342 deletions(-)
diffs (truncated from 2368 to 300 lines):
diff -r f4bbf8f7f628 -r f5d0618a4a1d sys/arch/arm/imx/files.imx51
--- a/sys/arch/arm/imx/files.imx51 Fri Jul 25 07:12:55 2014 +0000
+++ b/sys/arch/arm/imx/files.imx51 Fri Jul 25 07:49:56 2014 +0000
@@ -1,10 +1,11 @@
-# $NetBSD: files.imx51,v 1.10 2014/07/25 07:07:47 hkenken Exp $
+# $NetBSD: files.imx51,v 1.11 2014/07/25 07:49:56 hkenken Exp $
#
# Configuration info for the Freescale i.MX5x
#
defparam opt_imx.h MEMSIZE
defflag opt_imx.h IMX51
+defflag opt_imx.h IMX50
define bus_dma_generic
@@ -32,7 +33,8 @@
# Clock Control Module
device imxccm
attach imxccm at axi
-file arch/arm/imx/imx51_ccm.c imxccm needs-flag
+file arch/arm/imx/imx51_ccm.c imxccm needs-flag
+defflag opt_imx51clk.h IMXCCMDEBUG
# frequency of external low frequency clock
# typically 32000, 32768, or 38400.
@@ -63,6 +65,12 @@
attach imxiomux at axi
file arch/arm/imx/imx51_iomux.c imxiomux
+# EPDC controller
+# device epdc : bus_dma_generic, wsemuldisplaydev, rasops16, rasops8, rasops4, rasops_rotation, vcons
+# file arch/arm/imx/imx50_epdc.c epdc needs-flag
+# defflag opt_imx50_epdc.h IMXEPDCCONSOLE
+# defparam opt_imx50_epdc.h EPDC_DEBUG
+
# IPU v3 controller
device ipu : bus_dma_generic, wsemuldisplaydev, rasops16, rasops8, rasops4, rasops_rotation, vcons
file arch/arm/imx/imx51_ipuv3.c ipu needs-flag
diff -r f4bbf8f7f628 -r f5d0618a4a1d sys/arch/arm/imx/imx50_iomuxreg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/imx50_iomuxreg.h Fri Jul 25 07:49:56 2014 +0000
@@ -0,0 +1,563 @@
+/* $NetBSD: imx50_iomuxreg.h,v 1.1 2014/07/25 07:49:56 hkenken Exp $ */
+
+/*
+ * Copyright (c) 2012 Genetec Corporation. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file was generated automatically from PDF file by mkiomuxreg_imx50.rb
+ */
+
+#ifndef _ARM_IMX_IMX50_IOMUXREG_H
+#define _ARM_IMX_IMX50_IOMUXREG_H
+
+/* register offset address */
+
+#define IOMUXC_GPR0 0x0000
+#define IOMUXC_GPR1 0x0004
+#define IOMUXC_GPR2 0x0008
+#define IOMUXC_OBSERVE_MUX_0 0x000C
+#define IOMUXC_OBSERVE_MUX_1 0x0010
+#define IOMUXC_OBSERVE_MUX_2 0x0014
+#define IOMUXC_OBSERVE_MUX_3 0x0018
+#define IOMUXC_OBSERVE_MUX_4 0x001C
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x0020
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x0024
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x0028
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x002C
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x0030
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x0034
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x0038
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x003C
+#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL 0x0040
+#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA 0x0044
+#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL 0x0048
+#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA 0x004C
+#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL 0x0050
+#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA 0x0054
+#define IOMUXC_SW_MUX_CTL_PAD_PWM1 0x0058
+#define IOMUXC_SW_MUX_CTL_PAD_PWM2 0x005C
+#define IOMUXC_SW_MUX_CTL_PAD_OWIRE 0x0060
+#define IOMUXC_SW_MUX_CTL_PAD_EPITO 0x0064
+#define IOMUXC_SW_MUX_CTL_PAD_WDOG 0x0068
+#define IOMUXC_SW_MUX_CTL_PAD_SSI_TXFS 0x006C
+#define IOMUXC_SW_MUX_CTL_PAD_SSI_TXC 0x0070
+#define IOMUXC_SW_MUX_CTL_PAD_SSI_TXD 0x0074
+#define IOMUXC_SW_MUX_CTL_PAD_SSI_RXD 0x0078
+#define IOMUXC_SW_MUX_CTL_PAD_SSI_RXF 0x007C
+#define IOMUXC_SW_MUX_CTL_PAD_SSI_RXC 0x0080
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_TXD 0x0084
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RXD 0x0088
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_CTS 0x008C
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RTS 0x0090
+#define IOMUXC_SW_MUX_CTL_PAD_UART2_TXD 0x0094
+#define IOMUXC_SW_MUX_CTL_PAD_UART2_RXD 0x0098
+#define IOMUXC_SW_MUX_CTL_PAD_UART2_CTS 0x009C
+#define IOMUXC_SW_MUX_CTL_PAD_UART2_RTS 0x00A0
+#define IOMUXC_SW_MUX_CTL_PAD_UART3_TXD 0x00A4
+#define IOMUXC_SW_MUX_CTL_PAD_UART3_RXD 0x00A8
+#define IOMUXC_SW_MUX_CTL_PAD_UART4_TXD 0x00AC
+#define IOMUXC_SW_MUX_CTL_PAD_UART4_RXD 0x00B0
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI_SCLK 0x00B4
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI_MOSI 0x00B8
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI_MISO 0x00BC
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI_SS0 0x00C0
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK 0x00C4
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI 0x00C8
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO 0x00CC
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 0x00D0
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK 0x00D4
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI 0x00D8
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO 0x00DC
+#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 0x00E0
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK 0x00E4
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD 0x00E8
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_D0 0x00EC
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_D1 0x00F0
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_D2 0x00F4
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_D3 0x00F8
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK 0x00FC
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD 0x0100
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_D0 0x0104
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_D1 0x0108
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_D2 0x010C
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_D3 0x0110
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_D4 0x0114
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_D5 0x0118
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_D6 0x011C
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_D7 0x0120
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_WP 0x0124
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_CD 0x0128
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D0 0x012C
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D1 0x0130
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D2 0x0134
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D3 0x0138
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D4 0x013C
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D5 0x0140
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D6 0x0144
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D7 0x0148
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_WR 0x014C
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_RD 0x0150
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_RS 0x0154
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_CS 0x0158
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_BUSY 0x015C
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_RESET 0x0160
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD 0x0164
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK 0x0168
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_D0 0x016C
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_D1 0x0170
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_D2 0x0174
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_D3 0x0178
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_D4 0x017C
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_D5 0x0180
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_D6 0x0184
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_D7 0x0188
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_WP 0x018C
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D8 0x0190
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D9 0x0194
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D10 0x0198
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D11 0x019C
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D12 0x01A0
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D13 0x01A4
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D14 0x01A8
+#define IOMUXC_SW_MUX_CTL_PAD_DISP_D15 0x01AC
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D0 0x01B0
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D1 0x01B4
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D2 0x01B8
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D3 0x01BC
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D4 0x01C0
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D5 0x01C4
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D6 0x01C8
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D7 0x01CC
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D8 0x01D0
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D9 0x01D4
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D10 0x01D8
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D11 0x01DC
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D12 0x01E0
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D13 0x01E4
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D14 0x01E8
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_D15 0x01EC
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK 0x01F0
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP 0x01F4
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE 0x01F8
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL 0x01FC
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK 0x0200
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOEZ 0x0204
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOED 0x0208
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE 0x020C
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE 0x0210
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLKN 0x0214
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR 0x0218
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRCOM 0x021C
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRSTAT 0x0220
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRCTRL0 0x0224
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRCTRL1 0x0228
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRCTRL2 0x022C
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRCTRL3 0x0230
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_VCOM0 0x0234
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_VCOM1 0x0238
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0 0x023C
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1 0x0240
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0 0x0244
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1 0x0248
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2 0x024C
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3 0x0250
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE4 0x0254
+#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE5 0x0258
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA0 0x025C
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA1 0x0260
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA2 0x0264
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA3 0x0268
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA4 0x026C
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA5 0x0270
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA6 0x0274
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA7 0x0278
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA8 0x027C
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA9 0x0280
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA10 0x0284
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA11 0x0288
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA12 0x028C
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA13 0x0290
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA14 0x0294
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA15 0x0298
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS2 0x029C
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS1 0x02A0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS0 0x02A4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB0 0x02A8
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB1 0x02AC
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT 0x02B0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK 0x02B4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_RDY 0x02B8
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_OE 0x02BC
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_RW 0x02C0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_LBA 0x02C4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CRE 0x02C8
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 0x02CC
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 0x02D0
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 0x02D4
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 0x02D8
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 0x02DC
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 0x02E0
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 0x02E4
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 0x02E8
+#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL 0x02EC
+#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA 0x02F0
+#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL 0x02F4
+#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA 0x02F8
+#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL 0x02FC
+#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA 0x0300
+#define IOMUXC_SW_PAD_CTL_PAD_PWM1 0x0304
+#define IOMUXC_SW_PAD_CTL_PAD_PWM2 0x0308
+#define IOMUXC_SW_PAD_CTL_PAD_OWIRE 0x030C
+#define IOMUXC_SW_PAD_CTL_PAD_EPITO 0x0310
+#define IOMUXC_SW_PAD_CTL_PAD_WDOG 0x0314
+#define IOMUXC_SW_PAD_CTL_PAD_SSI_TXFS 0x0318
+#define IOMUXC_SW_PAD_CTL_PAD_SSI_TXC 0x031C
+#define IOMUXC_SW_PAD_CTL_PAD_SSI_TXD 0x0320
+#define IOMUXC_SW_PAD_CTL_PAD_SSI_RXD 0x0324
+#define IOMUXC_SW_PAD_CTL_PAD_SSI_RXFS 0x0328
+#define IOMUXC_SW_PAD_CTL_PAD_SSI_RXC 0x032C
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TXD 0x0330
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RXD 0x0334
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_CTS 0x0338
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RTS 0x033C
+#define IOMUXC_SW_PAD_CTL_PAD_UART2_TXD 0x0340
+#define IOMUXC_SW_PAD_CTL_PAD_UART2_RXD 0x0344
+#define IOMUXC_SW_PAD_CTL_PAD_UART2_CTS 0x0348
+#define IOMUXC_SW_PAD_CTL_PAD_UART2_RTS 0x034C
+#define IOMUXC_SW_PAD_CTL_PAD_UART3_TXD 0x0350
+#define IOMUXC_SW_PAD_CTL_PAD_UART3_RXD 0x0354
+#define IOMUXC_SW_PAD_CTL_PAD_UART4_TXD 0x0358
+#define IOMUXC_SW_PAD_CTL_PAD_UART4_RXD 0x035C
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI_SCLK 0x0360
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI_MOSI 0x0364
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI_MISO 0x0368
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI_SS0 0x036C
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