[src/trunk]: src/sys/dev/mii Add the following registers from IEEE 802.3-2009...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/e13c0e68feed
branches:  trunk
changeset: 786098:e13c0e68feed
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Mon Apr 15 08:09:48 2013 +0000

description:
Add the following registers from IEEE 802.3-2009 Clause 22.
 - PSE control register(0x0b)
 - PSE status register(0x0c)
 - MMD access control register(0x0d)
 - MMD access address data register(0x0e)

diffstat:

 sys/dev/mii/mii.h |  37 ++++++++++++++++++++++++++++++++++++-
 1 files changed, 36 insertions(+), 1 deletions(-)

diffs (51 lines):

diff -r a7c2acf9bb90 -r e13c0e68feed sys/dev/mii/mii.h
--- a/sys/dev/mii/mii.h Mon Apr 15 07:58:35 2013 +0000
+++ b/sys/dev/mii/mii.h Mon Apr 15 08:09:48 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mii.h,v 1.15 2013/04/03 03:24:27 msaitoh Exp $ */
+/*     $NetBSD: mii.h,v 1.16 2013/04/15 08:09:48 msaitoh Exp $ */
 
 /*
  * Copyright (c) 1997 Manuel Bouyer.  All rights reserved.
@@ -177,6 +177,41 @@
 #define        GTSR_LP_ASM_DIR 0x0200  /* link partner asym. pause dir. capable */
 #define        GTSR_IDLE_ERR   0x00ff  /* IDLE error count */
 
+#define        MII_PSECR       0x0b    /* PSE control register */
+#define        PSECR_PACTLMASK 0x000c  /* pair control mask */
+#define        PSECR_PSEENMASK 0x0003  /* PSE enable mask */
+#define        PSECR_PINOUTB   0x0008  /* PSE pinout Alternative B */
+#define        PSECR_PINOUTA   0x0004  /* PSE pinout Alternative A */
+#define        PSECR_FOPOWTST  0x0002  /* Force Power Test Mode */
+#define        PSECR_PSEEN     0x0001  /* PSE Enabled */
+#define        PSECR_PSEDIS    0x0000  /* PSE Disabled */
+
+#define        MII_PSESR       0x0c    /* PSE status register */
+#define        PSESR_PWRDENIED 0x1000  /* Power Deined */
+#define        PSESR_VALSIG    0x0800  /* Valid PD signature detected */
+#define        PSESR_INVALSIG  0x0400  /* Inalid PD signature detected */
+#define        PSESR_SHORTCIRC 0x0200  /* Short circuit condition detected */
+#define        PSESR_OVERLOAD  0x0100  /* Overload condition detected */
+#define        PSESR_MPSABSENT 0x0080  /* MPS absent condition detected */
+#define        PSESR_PDCLMASK  0x0070  /* PD Class mask */
+#define        PSESR_STATMASK  0x000e  /* PSE Status mask */
+#define        PSESR_PAIRCTABL 0x0001  /* PAIR Control Ability */
+#define        PSESR_PDCL_4            (4 << 4)        /* Class 4 */
+#define        PSESR_PDCL_3            (3 << 4)        /* Class 3 */
+#define        PSESR_PDCL_2            (2 << 4)        /* Class 2 */
+#define        PSESR_PDCL_1            (1 << 4)        /* Class 1 */
+#define        PSESR_PDCL_0            (0 << 4)        /* Class 0 */
+
+#define        MII_MMDACR      0x0d    /* MMD access control register */
+#define        MMDACR_FUNCMASK 0xc000  /* function */
+#define        MMDACR_DADDRMASK 0x001f /* device address */
+#define        MMDACR_FN_ADDRESS       (0 << 14) /* address */
+#define        MMDACR_FN_DATANPI       (1 << 14) /* data, no post increment */
+#define        MMDACR_FN_DATAPIRW      (2 << 14) /* data, post increment on r/w */
+#define        MMDACR_FN_DATAPIW       (3 << 14) /* data, post increment on wr only */
+
+#define        MII_MMDAADR     0x0e    /* MMD access address data register */
+
 #define        MII_EXTSR       0x0f    /* Extended status register */
 #define        EXTSR_1000XFDX  0x8000  /* 1000X full-duplex capable */
 #define        EXTSR_1000XHDX  0x4000  /* 1000X half-duplex capable */