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[src/trunk]: src/sys/dev/pci - Add slot related registers
details: https://anonhg.NetBSD.org/src/rev/df1716624131
branches: trunk
changeset: 786146:df1716624131
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Wed Apr 17 06:31:15 2013 +0000
description:
- Add slot related registers
- Add root port related registers
- Fix the definition of PCI_PCIE_SLCAP_PSN
- Cleanup
diffstat:
sys/dev/pci/pci_subr.c | 330 +++++++++++++++++++++++++++---------------------
sys/dev/pci/pcireg.h | 11 +-
2 files changed, 193 insertions(+), 148 deletions(-)
diffs (truncated from 532 to 300 lines):
diff -r 6f3a540156c4 -r df1716624131 sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c Wed Apr 17 06:12:42 2013 +0000
+++ b/sys/dev/pci/pci_subr.c Wed Apr 17 06:31:15 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.100 2013/04/17 04:36:27 msaitoh Exp $ */
+/* $NetBSD: pci_subr.c,v 1.101 2013/04/17 06:31:15 msaitoh Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.100 2013/04/17 04:36:27 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.101 2013/04/17 06:31:15 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -859,18 +859,20 @@
static void
pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
{
- pcireg_t val;
+ pcireg_t reg; /* for each register */
+ pcireg_t val; /* for each bitfield */
bool check_slot = false;
+ bool check_rootport = false;
static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"};
printf("\n PCI Express Capabilities Register\n");
/* Capability Register */
- printf(" Capability register: %04x\n",
- regs[o2i(capoff)] >> 16);
+ reg = regs[o2i(capoff)];
+ printf(" Capability register: %04x\n", reg >> 16);
printf(" Capability version: %x\n",
- (unsigned int)((regs[o2i(capoff)] & 0x000f0000) >> 16));
+ (unsigned int)((reg & 0x000f0000) >> 16));
printf(" Device type: ");
- switch ((regs[o2i(capoff)] & 0x00f00000) >> 20) {
+ switch ((reg & 0x00f00000) >> 20) {
case 0x0:
printf("PCI Express Endpoint device\n");
break;
@@ -880,6 +882,7 @@
case 0x4:
printf("Root Port of PCI Express Root Complex\n");
check_slot = true;
+ check_rootport = true; /* XXX right? */
break;
case 0x5:
printf("Upstream Port of PCI Express Switch\n");
@@ -887,6 +890,7 @@
case 0x6:
printf("Downstream Port of PCI Express Switch\n");
check_slot = true;
+ check_rootport = true; /* XXX right? */
break;
case 0x7:
printf("PCI Express to PCI/PCI-X Bridge\n");
@@ -896,6 +900,7 @@
break;
case 0x9:
printf("Root Complex Integrated Endpoint\n");
+ check_rootport = true; /* XXX right? */
break;
case 0xa:
printf("Root Complex Event Collector\n");
@@ -904,20 +909,18 @@
printf("unknown\n");
break;
}
- if (check_slot && (regs[o2i(capoff)] & 0x01000000) != 0)
+ if (check_slot && (reg & PCI_PCIE_XCAP_SI) != 0)
printf(" Slot implemented\n");
printf(" Interrupt Message Number: %x\n",
- (unsigned int)((regs[o2i(capoff)] & PCI_PCIE_XCAP_IRQ) >> 27));
+ (unsigned int)((reg & PCI_PCIE_XCAP_IRQ) >> 27));
/* Device Capability Register */
- printf(" Device Capabilities Register: 0x%08x\n",
- regs[o2i(capoff + PCI_PCIE_DCAP)]);
+ reg = regs[o2i(capoff + PCI_PCIE_DCAP)];
+ printf(" Device Capabilities Register: 0x%08x\n", reg);
printf(" Max Payload Size Supported: %u bytes max\n",
- (unsigned int)(regs[o2i(capoff + PCI_PCIE_DCAP)]
- & PCI_PCIE_DCAP_MAX_PAYLOAD) * 256);
+ (unsigned int)(reg & PCI_PCIE_DCAP_MAX_PAYLOAD) * 256);
printf(" Phantom Functions Supported: ");
- switch ((regs[o2i(capoff + PCI_PCIE_DCAP)]
- & PCI_PCIE_DCAP_PHANTOM_FUNCS) >> 3) {
+ switch ((reg & PCI_PCIE_DCAP_PHANTOM_FUNCS) >> 3) {
case 0x0:
printf("not available\n");
break;
@@ -932,112 +935,82 @@
break;
}
printf(" Extended Tag Field Supported: %dbit\n",
- (regs[o2i(capoff + PCI_PCIE_DCAP)] & PCI_PCIE_DCAP_EXT_TAG_FIELD)
- == 0 ? 5 : 8);
+ (reg & PCI_PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8);
printf(" Endpoint L0 Acceptable Latency: ");
- pci_print_pcie_L0s_latency((regs[o2i(capoff + PCI_PCIE_DCAP)]
- & PCI_PCIE_DCAP_L0S_LATENCY) >> 6);
+ pci_print_pcie_L0s_latency((reg & PCI_PCIE_DCAP_L0S_LATENCY) >> 6);
printf(" Endpoint L1 Acceptable Latency: ");
- pci_print_pcie_L1_latency((regs[o2i(capoff + PCI_PCIE_DCAP)]
- & PCI_PCIE_DCAP_L1_LATENCY) >> 9);
+ pci_print_pcie_L1_latency((reg & PCI_PCIE_DCAP_L1_LATENCY) >> 9);
printf(" Attention Button Present: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCAP)]
- & PCI_PCIE_DCAP_ATTN_BUTTON) != 0 ? "yes" : "no");
+ (reg & PCI_PCIE_DCAP_ATTN_BUTTON) != 0 ? "yes" : "no");
printf(" Attention Indicator Present: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCAP)]
- & PCI_PCIE_DCAP_ATTN_IND) != 0 ? "yes" : "no");
+ (reg & PCI_PCIE_DCAP_ATTN_IND) != 0 ? "yes" : "no");
printf(" Power Indicator Present: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCAP)]
- & PCI_PCIE_DCAP_PWR_IND) != 0 ? "yes" : "no");
+ (reg & PCI_PCIE_DCAP_PWR_IND) != 0 ? "yes" : "no");
printf(" Role-Based Error Report: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCAP)]
- & PCI_PCIE_DCAP_ROLE_ERR_RPT) != 0 ? "yes" : "no");
+ (reg & PCI_PCIE_DCAP_ROLE_ERR_RPT) != 0 ? "yes" : "no");
printf(" Captured Slot Power Limit Value: %d\n",
- (unsigned int)(regs[o2i(capoff + PCI_PCIE_DCAP)]
- & PCI_PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18);
+ (unsigned int)(reg & PCI_PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18);
printf(" Captured Slot Power Limit Scale: %d\n",
- (unsigned int)(regs[o2i(capoff + PCI_PCIE_DCAP)]
- & PCI_PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26);
+ (unsigned int)(reg & PCI_PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26);
printf(" Function-Level Reset Capability: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCAP)]
- & PCI_PCIE_DCAP_FLR) != 0 ? "yes" : "no");
+ (reg & PCI_PCIE_DCAP_FLR) != 0 ? "yes" : "no");
/* Device Control Register */
- printf(" Device Control Register: 0x%04x\n",
- regs[o2i(capoff + PCI_PCIE_DCSR)] & 0xffff);
+ reg = regs[o2i(capoff + PCI_PCIE_DCSR)];
+ printf(" Device Control Register: 0x%04x\n", reg & 0xffff);
printf(" Correctable Error Reporting Enable: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCSR)]
- & PCI_PCIE_DCSR_ENA_COR_ERR) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_DCSR_ENA_COR_ERR) != 0 ? "on" : "off");
printf(" Non Fatal Error Reporting Enable: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCSR)]
- & PCI_PCIE_DCSR_ENA_NFER) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_DCSR_ENA_NFER) != 0 ? "on" : "off");
printf(" Fatal Error Reporting Enable: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCSR)]
- & PCI_PCIE_DCSR_ENA_FER) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_DCSR_ENA_FER) != 0 ? "on" : "off");
printf(" Unsupported Request Reporting Enable: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCSR)]
- & PCI_PCIE_DCSR_ENA_URR) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_DCSR_ENA_URR) != 0 ? "on" : "off");
printf(" Enable Relaxed Ordering: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCSR)]
- & PCI_PCIE_DCSR_ENA_RELAX_ORD) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_DCSR_ENA_RELAX_ORD) != 0 ? "on" : "off");
printf(" Max Payload Size: %d byte\n",
- 128 << (((unsigned int)(regs[o2i(capoff + PCI_PCIE_DCSR)]
- & PCI_PCIE_DCSR_MAX_PAYLOAD) >> 5)));
+ 128 << (((unsigned int)(reg & PCI_PCIE_DCSR_MAX_PAYLOAD) >> 5)));
printf(" Extended Tag Field Enable: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCSR)]
- & PCI_PCIE_DCSR_EXT_TAG_FIELD) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_DCSR_EXT_TAG_FIELD) != 0 ? "on" : "off");
printf(" Phantom Functions Enable: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCSR)]
- & PCI_PCIE_DCSR_PHANTOM_FUNCS) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_DCSR_PHANTOM_FUNCS) != 0 ? "on" : "off");
printf(" Aux Power PM Enable: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCSR)]
- & PCI_PCIE_DCSR_AUX_POWER_PM) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_DCSR_AUX_POWER_PM) != 0 ? "on" : "off");
printf(" Enable No Snoop: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCSR)]
- & PCI_PCIE_DCSR_ENA_NO_SNOOP) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_DCSR_ENA_NO_SNOOP) != 0 ? "on" : "off");
printf(" Max Read Request Size: %d byte\n",
- 128 << ((unsigned int)(regs[o2i(capoff + PCI_PCIE_DCSR)]
- & PCI_PCIE_DCSR_MAX_READ_REQ) >> 12));
+ 128 << ((unsigned int)(reg & PCI_PCIE_DCSR_MAX_READ_REQ) >> 12));
/* Device Status Register */
- printf(" Device Status Register: 0x%04x\n",
- regs[o2i(capoff + PCI_PCIE_DCSR)] >> 16);
+ reg = regs[o2i(capoff + PCI_PCIE_DCSR)];
+ printf(" Device Status Register: 0x%04x\n", reg >> 16);
printf(" Correctable Error Detected: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCSR)]
- & PCI_PCIE_DCSR_CED) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_DCSR_CED) != 0 ? "on" : "off");
printf(" Non Fatal Error Detected: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCSR)]
- & PCI_PCIE_DCSR_NFED) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_DCSR_NFED) != 0 ? "on" : "off");
printf(" Fatal Error Detected: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCSR)]
- & PCI_PCIE_DCSR_FED) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_DCSR_FED) != 0 ? "on" : "off");
printf(" Unsupported Request Detected: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCSR)]
- & PCI_PCIE_DCSR_URD) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_DCSR_URD) != 0 ? "on" : "off");
printf(" Aux Power Detected: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCSR)]
- & PCI_PCIE_DCSR_AUX_PWR) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_DCSR_AUX_PWR) != 0 ? "on" : "off");
printf(" Transaction Pending: %s\n",
- (regs[o2i(capoff + PCI_PCIE_DCSR)]
- & PCI_PCIE_DCSR_TRANSACTION_PND) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_DCSR_TRANSACTION_PND) != 0 ? "on" : "off");
/* Link Capability Register */
- printf(" Link Capabilities Register: 0x%08x\n",
- regs[o2i(capoff + PCI_PCIE_LCAP)]);
+ reg = regs[o2i(capoff + PCI_PCIE_LCAP)];
+ printf(" Link Capabilities Register: 0x%08x\n", reg);
printf(" Maximum Link Speed: ");
- if ((regs[o2i(capoff + PCI_PCIE_LCAP)] & 0x000f) < 1 ||
- (regs[o2i(capoff + PCI_PCIE_LCAP)] & 0x000f) > 3) {
- printf("unknown %u value\n",
- (regs[o2i(capoff + PCI_PCIE_LCAP)] & 0x000f));
+ val = reg & PCI_PCIE_LCAP_MAX_SPEED;
+ if (val < 1 || val > 3) {
+ printf("unknown %u value\n", val);
} else {
- printf("%sGb/s\n",
- linkspeeds[(regs[o2i(capoff + PCI_PCIE_LCAP)] & 0x000f)
- - 1]);
+ printf("%sGb/s\n", linkspeeds[val - 1]);
}
printf(" Maximum Link Width: x%u lanes\n",
- (regs[o2i(capoff + PCI_PCIE_LCAP)] & 0x03f0) >> 4);
+ (unsigned int)(reg & PCI_PCIE_LCAP_MAX_WIDTH) >> 4);
printf(" Active State PM Support: ");
- val = (regs[o2i(capoff + PCI_PCIE_LCAP)] & PCI_PCIE_LCAP_ASPM) >> 10;
+ val = (reg & PCI_PCIE_LCAP_ASPM) >> 10;
switch (val) {
case 0x1:
printf("L0s Entry supported\n");
@@ -1050,20 +1023,16 @@
break;
}
printf(" L0 Exit Latency: ");
- pci_print_pcie_L0s_latency((regs[o2i(capoff + PCI_PCIE_LCAP)]
- & PCI_PCIE_LCAP_L0S_EXIT) >> 12);
+ pci_print_pcie_L0s_latency((reg & PCI_PCIE_LCAP_L0S_EXIT) >> 12);
printf(" L1 Exit Latency: ");
- pci_print_pcie_L1_latency((regs[o2i(capoff + PCI_PCIE_LCAP)]
- & PCI_PCIE_LCAP_L1_EXIT) >> 15);
- printf(" Port Number: %u\n",
- regs[o2i(capoff + PCI_PCIE_LCAP)] >> 24);
+ pci_print_pcie_L1_latency((reg & PCI_PCIE_LCAP_L1_EXIT) >> 15);
+ printf(" Port Number: %u\n", reg >> 24);
/* Link Control Register */
- printf(" Link Control Register: 0x%04x\n",
- regs[o2i(capoff + PCI_PCIE_LCSR)] & 0xffff);
+ reg = regs[o2i(capoff + PCI_PCIE_LCSR)];
+ printf(" Link Control Register: 0x%04x\n", reg & 0xffff);
printf(" Active State PM Control: ");
- val = regs[o2i(capoff + PCI_PCIE_LCSR)]
- & (PCI_PCIE_LCSR_ASPM_L1 | PCI_PCIE_LCSR_ASPM_L0S);
+ val = reg & (PCI_PCIE_LCSR_ASPM_L1 | PCI_PCIE_LCSR_ASPM_L0S);
switch (val) {
case 0:
printf("disabled\n");
@@ -1079,84 +1048,99 @@
break;
}
printf(" Read Completion Boundary Control: %dbyte\n",
- (regs[o2i(capoff + PCI_PCIE_LCSR)]
- & PCI_PCIE_LCSR_RCB) != 0 ? 128 : 64);
+ (reg & PCI_PCIE_LCSR_RCB) != 0 ? 128 : 64);
printf(" Link Disable: %s\n",
- (regs[o2i(capoff + PCI_PCIE_LCSR)]
- & PCI_PCIE_LCSR_LINK_DIS) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_LCSR_LINK_DIS) != 0 ? "on" : "off");
printf(" Retrain Link: %s\n",
- (regs[o2i(capoff + PCI_PCIE_LCSR)]
- & PCI_PCIE_LCSR_RETRAIN) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_LCSR_RETRAIN) != 0 ? "on" : "off");
printf(" Common Clock Configuration: %s\n",
- (regs[o2i(capoff + PCI_PCIE_LCSR)]
- & PCI_PCIE_LCSR_COMCLKCFG) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_LCSR_COMCLKCFG) != 0 ? "on" : "off");
printf(" Extended Synch: %s\n",
- (regs[o2i(capoff + PCI_PCIE_LCSR)]
- & PCI_PCIE_LCSR_EXTNDSYNC) != 0 ? "on" : "off");
+ (reg & PCI_PCIE_LCSR_EXTNDSYNC) != 0 ? "on" : "off");
printf(" Enable Clock Power Management: %s\n",
- (regs[o2i(capoff + PCI_PCIE_LCSR)]
- & PCI_PCIE_LCSR_ENCLKPM) != 0 ? "on" : "off");
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