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[src/trunk]: src/sys/arch Don't use cpsr_all/spsr_all with mrs, it doesn't ta...
details: https://anonhg.NetBSD.org/src/rev/f912bc2cbe96
branches: trunk
changeset: 791803:f912bc2cbe96
user: joerg <joerg%NetBSD.org@localhost>
date: Mon Dec 02 18:36:10 2013 +0000
description:
Don't use cpsr_all/spsr_all with mrs, it doesn't take a mask.
diffstat:
sys/arch/arm/arm/cpufunc_asm_arm8.S | 8 ++++----
sys/arch/arm/arm/cpufunc_asm_sa1.S | 6 +++---
sys/arch/arm/arm/cpufunc_asm_sa11x0.S | 4 ++--
sys/arch/arm/arm/cpufunc_asm_xscale.S | 6 +++---
sys/arch/arm/arm/fiq_subr.S | 4 ++--
sys/arch/arm/arm32/exception.S | 8 ++++----
sys/arch/arm/arm32/spl.S | 10 +++++-----
sys/arch/arm/include/arm32/frame.h | 14 +++++++-------
sys/arch/arm/iomd/iomd_irq.S | 8 ++++----
sys/arch/arm/ofw/ofw_irq.S | 8 ++++----
sys/arch/arm/sa11x0/sa11x0_irq.S | 8 ++++----
sys/arch/evbarm/ixm1200/ixm1200_start.S | 6 +++---
sys/arch/hpcarm/hpcarm/locore.S | 6 +++---
sys/arch/hpcarm/hpcarm/softintr.c | 8 ++++----
sys/arch/hpcarm/hpcarm/spl.S | 8 ++++----
sys/arch/shark/isa/isa_irq.S | 8 ++++----
sys/arch/zaurus/stand/zbsdmod/zbsdmod.c | 4 ++--
17 files changed, 62 insertions(+), 62 deletions(-)
diffs (truncated from 548 to 300 lines):
diff -r 4f1d89a20513 -r f912bc2cbe96 sys/arch/arm/arm/cpufunc_asm_arm8.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm8.S Mon Dec 02 15:54:06 2013 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm8.S Mon Dec 02 18:36:10 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm8.S,v 1.8 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: cpufunc_asm_arm8.S,v 1.9 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 1997 ARM Limited
@@ -65,7 +65,7 @@
* addresses that are about to change.
*/
ENTRY(arm8_setttb)
- mrs r3, cpsr_all
+ mrs r3, cpsr
orr r2, r3, #(I32_bit | F32_bit)
msr cpsr_all, r2
@@ -176,7 +176,7 @@
mov r0, #0x00000000
- mrs r3, cpsr_all
+ mrs r3, cpsr
orr r2, r3, #(I32_bit | F32_bit)
msr cpsr_all, r2
@@ -248,7 +248,7 @@
* mcr p15, 0, rd, c7, c11, 1
* mcr p15, 0, rd, c7, c7, 1
*/
- mrs r3, cpsr_all
+ mrs r3, cpsr
orr r2, r3, #(I32_bit | F32_bit)
msr cpsr_all, r2
mcr p15, 0, r0, c7, c11, 1 /* clean I+D single entry */
diff -r 4f1d89a20513 -r f912bc2cbe96 sys/arch/arm/arm/cpufunc_asm_sa1.S
--- a/sys/arch/arm/arm/cpufunc_asm_sa1.S Mon Dec 02 15:54:06 2013 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_sa1.S Mon Dec 02 18:36:10 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_sa1.S,v 1.13 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: cpufunc_asm_sa1.S,v 1.14 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 1997,1998 Mark Brinicombe.
@@ -49,7 +49,7 @@
*/
ENTRY(sa1_setttb)
#ifdef CACHE_CLEAN_BLOCK_INTR
- mrs r3, cpsr_all
+ mrs r3, cpsr
orr r2, r3, #(I32_bit | F32_bit)
msr cpsr_all, r2
#else
@@ -146,7 +146,7 @@
#ifdef CACHE_CLEAN_BLOCK_INTR
#define SA1_CACHE_CLEAN_BLOCK \
- mrs r3, cpsr_all ; \
+ mrs r3, cpsr ; \
orr r0, r3, #(I32_bit | F32_bit) ; \
msr cpsr_all, r0
diff -r 4f1d89a20513 -r f912bc2cbe96 sys/arch/arm/arm/cpufunc_asm_sa11x0.S
--- a/sys/arch/arm/arm/cpufunc_asm_sa11x0.S Mon Dec 02 15:54:06 2013 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_sa11x0.S Mon Dec 02 18:36:10 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_sa11x0.S,v 1.4 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: cpufunc_asm_sa11x0.S,v 1.5 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@@ -79,7 +79,7 @@
* re-enable clock switching before servicing interrupts.
*/
- mrs r3, cpsr_all /* 6 */
+ mrs r3, cpsr /* 6 */
orr r2, r3, #(I32_bit|F32_bit) /* 7 */
msr cpsr_all, r2 /* 8 */
diff -r 4f1d89a20513 -r f912bc2cbe96 sys/arch/arm/arm/cpufunc_asm_xscale.S
--- a/sys/arch/arm/arm/cpufunc_asm_xscale.S Mon Dec 02 15:54:06 2013 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_xscale.S Mon Dec 02 18:36:10 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_xscale.S,v 1.21 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: cpufunc_asm_xscale.S,v 1.22 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -133,7 +133,7 @@
*/
ENTRY(xscale_setttb)
#ifdef CACHE_CLEAN_BLOCK_INTR
- mrs r3, cpsr_all
+ mrs r3, cpsr
orr r2, r3, #(I32_bit | F32_bit)
msr cpsr_all, r2
#else
@@ -273,7 +273,7 @@
#ifdef CACHE_CLEAN_BLOCK_INTR
#define XSCALE_CACHE_CLEAN_BLOCK \
- mrs r3, cpsr_all ; \
+ mrs r3, cpsr ; \
orr r0, r3, #(I32_bit | F32_bit) ; \
msr cpsr_all, r0
diff -r 4f1d89a20513 -r f912bc2cbe96 sys/arch/arm/arm/fiq_subr.S
--- a/sys/arch/arm/arm/fiq_subr.S Mon Dec 02 15:54:06 2013 +0000
+++ b/sys/arch/arm/arm/fiq_subr.S Mon Dec 02 18:36:10 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: fiq_subr.S,v 1.5 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: fiq_subr.S,v 1.6 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -57,7 +57,7 @@
cps #PSR_FIQ32_MODE
#else
#define SWITCH_TO_FIQ_MODE \
- mrs r2, cpsr_all ; \
+ mrs r2, cpsr ; \
mov r3, r2 ; \
bic r2, r2, #(PSR_MODE) ; \
orr r2, r2, #(PSR_FIQ32_MODE) ; \
diff -r 4f1d89a20513 -r f912bc2cbe96 sys/arch/arm/arm32/exception.S
--- a/sys/arch/arm/arm32/exception.S Mon Dec 02 15:54:06 2013 +0000
+++ b/sys/arch/arm/arm32/exception.S Mon Dec 02 18:36:10 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: exception.S,v 1.19 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: exception.S,v 1.20 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
@@ -51,7 +51,7 @@
#include <arm/locore.h>
- RCSID("$NetBSD: exception.S,v 1.19 2013/08/18 06:28:18 matt Exp $")
+ RCSID("$NetBSD: exception.S,v 1.20 2013/12/02 18:36:10 joerg Exp $")
.text
.align 0
@@ -178,8 +178,8 @@
* it like a Data Abort.
*/
ASENTRY_NP(address_exception_entry)
- mrs r1, cpsr_all
- mrs r2, spsr_all
+ mrs r1, cpsr
+ mrs r2, spsr
mov r3, lr
adr r0, .Laddress_exception_msg
bl _C_LABEL(printf) /* XXX CLOBBERS LR!! */
diff -r 4f1d89a20513 -r f912bc2cbe96 sys/arch/arm/arm32/spl.S
--- a/sys/arch/arm/arm32/spl.S Mon Dec 02 15:54:06 2013 +0000
+++ b/sys/arch/arm/arm32/spl.S Mon Dec 02 18:36:10 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: spl.S,v 1.9 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: spl.S,v 1.10 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 1996-1998 Mark Brinicombe.
@@ -43,7 +43,7 @@
#include <arm/locore.h>
#include <arm/arm32/psl.h>
- RCSID("$NetBSD: spl.S,v 1.9 2013/08/18 06:28:18 matt Exp $")
+ RCSID("$NetBSD: spl.S,v 1.10 2013/12/02 18:36:10 joerg Exp $")
.text
.align 0
@@ -61,7 +61,7 @@
stmfd sp!, {r0, r1, r4, lr} /* Preserve registers */
/* Disable interrupts */
- mrs r4, cpsr_all
+ mrs r4, cpsr
orr r2, r4, #(I32_bit)
msr cpsr_c, r2
@@ -81,7 +81,7 @@
stmfd sp!, {r0, r1, r4, lr} /* Preserve registers */
/* Disable interrupts */
- mrs r4, cpsr_all
+ mrs r4, cpsr
orr r2, r4, #(I32_bit)
msr cpsr_c, r2
@@ -104,7 +104,7 @@
stmfd sp!, {r0, r1, r4, lr}
/* Disable interrupts */
- mrs r4, cpsr_all
+ mrs r4, cpsr
orr r2, r4, #(I32_bit)
msr cpsr_c, r2
diff -r 4f1d89a20513 -r f912bc2cbe96 sys/arch/arm/include/arm32/frame.h
--- a/sys/arch/arm/include/arm32/frame.h Mon Dec 02 15:54:06 2013 +0000
+++ b/sys/arch/arm/include/arm32/frame.h Mon Dec 02 18:36:10 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: frame.h,v 1.36 2013/08/18 06:37:02 matt Exp $ */
+/* $NetBSD: frame.h,v 1.37 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
@@ -351,7 +351,7 @@
sub sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \
PUSHUSERREGS; /* Push the user mode registers */ \
mov r0, r0; /* NOP for previous instruction */ \
- mrs r0, spsr_all; /* Get the SPSR */ \
+ mrs r0, spsr; /* Get the SPSR */ \
str r0, [sp, #-TF_R0]! /* Push the SPSR on the stack */
/*
@@ -364,7 +364,7 @@
str lr, [sp, #-4]!; /* save SVC32 lr */ \
str r6, [sp, #(TF_R6-TF_PC)]!; /* save callee-saved r6 */ \
str r4, [sp, #(TF_R4-TF_R6)]!; /* save callee-saved r4 */ \
- mrs r0, cpsr_all; /* Get the CPSR */ \
+ mrs r0, cpsr; /* Get the CPSR */ \
str r0, [sp, #(-TF_R4)]! /* Push the CPSR on the stack */
/*
@@ -378,7 +378,7 @@
str ip, [sp, #TF_SVC_SP]; \
str lr, [sp, #TF_SVC_LR]; \
str lr, [sp, #TF_PC]; \
- mrs rX, cpsr_all; /* Get the CPSR */ \
+ mrs rX, cpsr; /* Get the CPSR */ \
str rX, [sp, #TF_SPSR] /* save in trapframe */
#define PUSHSWITCHFRAME1 \
@@ -394,13 +394,13 @@
#define PUSHSWITCHFRAME2 \
strd r10, [sp, #TF_R10]; /* save r10 & r11 */ \
strd r8, [sp, #TF_R8]; /* save r8 & r9 */ \
- mrs r0, cpsr_all; /* Get the CPSR */ \
+ mrs r0, cpsr; /* Get the CPSR */ \
str r0, [sp, #TF_SPSR] /* save in trapframe */
#else
#define PUSHSWITCHFRAME2 \
add r0, sp, #TF_R8; /* get ptr to r8 and above */ \
stmia r0, {r8-r11}; /* save rest of registers */ \
- mrs r0, cpsr_all; /* Get the CPSR */ \
+ mrs r0, cpsr; /* Get the CPSR */ \
str r0, [sp, #TF_SPSR] /* save in trapframe */
#endif
@@ -469,7 +469,7 @@
sub sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \
PUSHUSERREGS; /* Push the user mode registers */ \
mov r0, r0; /* NOP for previous instruction */ \
- mrs r0, spsr_all; /* Get the SPSR */ \
+ mrs r0, spsr; /* Get the SPSR */ \
str r0, [sp, #-TF_R0]! /* Push the SPSR onto the stack */
/*
diff -r 4f1d89a20513 -r f912bc2cbe96 sys/arch/arm/iomd/iomd_irq.S
--- a/sys/arch/arm/iomd/iomd_irq.S Mon Dec 02 15:54:06 2013 +0000
+++ b/sys/arch/arm/iomd/iomd_irq.S Mon Dec 02 18:36:10 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: iomd_irq.S,v 1.15 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: iomd_irq.S,v 1.16 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@@ -208,7 +208,7 @@
/* Update the IOMD irq masks */
bl _C_LABEL(irq_setmasks)
- mrs r0, cpsr_all /* Enable IRQ's */
+ mrs r0, cpsr /* Enable IRQ's */
bic r0, r0, #I32_bit
msr cpsr_all, r0
@@ -331,7 +331,7 @@
#endif
/* Kill IRQ's in preparation for exit */
- mrs r0, cpsr_all
+ mrs r0, cpsr
orr r0, r0, #(I32_bit)
msr cpsr_all, r0
@@ -354,7 +354,7 @@
ENTRY(irq_setmasks)
/* Disable interrupts */
- mrs r3, cpsr_all
+ mrs r3, cpsr
orr r1, r3, #(I32_bit)
msr cpsr_all, r1
diff -r 4f1d89a20513 -r f912bc2cbe96 sys/arch/arm/ofw/ofw_irq.S
--- a/sys/arch/arm/ofw/ofw_irq.S Mon Dec 02 15:54:06 2013 +0000
+++ b/sys/arch/arm/ofw/ofw_irq.S Mon Dec 02 18:36:10 2013 +0000
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